chengyinwu / QuteRTL
QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification
☆15Updated 8 years ago
Alternatives and similar repositories for QuteRTL:
Users that are interested in QuteRTL are comparing it to the libraries listed below
- ☆16Updated 4 years ago
- ☆12Updated 4 years ago
- ☆15Updated 2 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆29Updated 9 months ago
- ☆14Updated last year
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 3 years ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆15Updated 6 years ago
- Hardware Formal Verification☆15Updated 4 years ago
- ☆13Updated 4 years ago
- ☆12Updated 2 years ago
- The PE for the second generation CGRA (garnet).☆17Updated last week
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆19Updated 4 months ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆30Updated last year
- The ANUBIS benchmark suite for Incremental Synthesis☆12Updated 4 years ago
- This is a python repo for flattening Verilog☆16Updated 3 weeks ago
- C++ parsing library for simple formats used in logic synthesis and formal verification☆36Updated 10 months ago
- Collection for submission (Hardware Model Checking Benchmark)☆9Updated 6 months ago
- ☆25Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆55Updated this week
- Fast Symbolic Repair of Hardware Design Code☆22Updated 3 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆13Updated last month
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆18Updated 11 months ago
- ☆19Updated 9 months ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆21Updated 3 months ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- ☆10Updated 5 years ago
- ☆13Updated 10 months ago
- ☆11Updated 3 years ago
- RISC-V Formal in Chisel☆11Updated last year