Alternatives and similar repositories for Riallto

Users that are interested in Riallto are comparing it to the libraries listed below

• nod-ai / iree-amd-aie
  IREE plugin repository for the AMD AIE accelerator
  ☆101Updated 2 weeks ago
• Xilinx / mlir-air
  ☆104Updated this week
• DeepWok / mase
  Machine-Learning Accelerator System Exploration Tools
  ☆173Updated 2 months ago
• ucb-bar / onnxruntime-riscv
  Fork of upstream onnxruntime focused on supporting risc-v accelerators
  ☆87Updated 2 years ago
• Xilinx / llvm-aie
  Fork of LLVM to support AMD AIEngine processors
  ☆156Updated this week
• Xilinx / ACCL
  Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators
  ☆97Updated last month
• Xilinx / xup_aie_training
  Hands-on experience programming AI Engines using Vitis Unified Software Platform
  ☆41Updated last year
• pulp-platform / occamy
  A high-efficiency system-on-chip for floating-point compute workloads.
  ☆40Updated 7 months ago
• arc-research-lab / Aries
  ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)
  ☆37Updated last week
• cornell-zhang / hcl-dialect
  HeteroCL-MLIR dialect for accelerator design
  ☆41Updated 11 months ago
• MartaAndronic / NeuraLUT
  NeuraLUT-Assemble
  ☆38Updated this week
• HLSTransform / submission
  ☆99Updated last year
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆38Updated 3 weeks ago
• kachris / survey_HA_LLM
  A survey on Hardware Accelerated LLMs
  ☆59Updated 7 months ago
• StanfordAHA / aha
  ☆60Updated this week
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆80Updated 6 years ago
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆131Updated last year
• esa-tu-darmstadt / spn-compiler
  Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.
  ☆24Updated 8 months ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆59Updated last year
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 5 years ago
• IAMAl / ML-Hardware-Collections
  News and Paper Collections for Machine Learning Hardware
  ☆22Updated last year
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆97Updated last year
• UCLA-VAST / Stream-HLS
  An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs
  ☆44Updated 3 weeks ago
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆108Updated 2 years ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆111Updated last year
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆31Updated 10 years ago
• cupbop / CuPBoP
  A framework that support executing unmodified CUDA source code on non-NVIDIA devices.
  ☆132Updated 7 months ago
• Xilinx / xacc
  Heterogeneous Accelerated Computed Cluster (HACC) Resources Page
  ☆22Updated 3 weeks ago
• cornell-zhang / heterocl
  HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
  ☆340Updated last year
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆41Updated 2 months ago