Alternatives and similar repositories for Riallto

Users that are interested in Riallto are comparing it to the libraries listed below

• nod-ai / iree-amd-aie
  IREE plugin repository for the AMD AIE accelerator
  ☆119Updated last week
• Xilinx / mlir-air
  ☆123Updated this week
• Xilinx / llvm-aie
  Fork of LLVM to support AMD AIEngine processors
  ☆187Updated this week
• DeepWok / mase
  Machine-Learning Accelerator System Exploration Tools
  ☆198Updated this week
• ucb-bar / onnxruntime-riscv
  Fork of upstream onnxruntime focused on supporting risc-v accelerators
  ☆88Updated 2 years ago
• Xilinx / ACCL
  Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators
  ☆101Updated 7 months ago
• HLSTransform / submission
  ☆119Updated 2 years ago
• arc-research-lab / Aries
  ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)
  ☆57Updated this week
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆131Updated last year
• kachris / survey_HA_LLM
  A survey on Hardware Accelerated LLMs
  ☆61Updated last year
• cupbop / CuPBoP
  A framework that support executing unmodified CUDA source code on non-NVIDIA devices.
  ☆141Updated last year
• IAMAl / ML-Hardware-Collections
  News and Paper Collections for Machine Learning Hardware
  ☆22Updated 2 months ago
• CMU-SAFARI / SPARTA
  A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…
  ☆22Updated 2 years ago
• Xilinx / xup_aie_training
  Hands-on experience programming AI Engines using Vitis Unified Software Platform
  ☆40Updated last year
• cornell-zhang / hcl-dialect
  HeteroCL-MLIR dialect for accelerator design
  ☆42Updated last year
• esa-tu-darmstadt / spn-compiler
  Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.
  ☆25Updated last year
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆40Updated 6 months ago
• UCLA-VAST / Stream-HLS
  An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs
  ☆58Updated 6 months ago
• cornell-zhang / heterocl
  HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)
  ☆342Updated last year
• Xilinx / XRM
  XRM (Xilinx FPGA Resource Manager) Document:
  ☆25Updated 2 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆83Updated 7 years ago
• pulp-platform / occamy
  A high-efficiency system-on-chip for floating-point compute workloads.
  ☆44Updated last year
• MartaAndronic / NeuraLUT
  NeuraLUT-Assemble
  ☆47Updated 5 months ago
• fastmachinelearning / qonnx
  QONNX: Arbitrary-Precision Quantized Neural Networks in ONNX
  ☆175Updated this week
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• cucapra / EventQueue
  EQueue Dialect
  ☆42Updated 4 years ago
• escalab / GPTPU
  GPTPU for SC 2021
  ☆52Updated 2 years ago
• PSAL-POSTECH / ONNXim
  ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference
  ☆184Updated last month
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆59Updated last year
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆118Updated 2 years ago