Alternatives and similar repositories for fpga-network-stack

Users that are interested in fpga-network-stack are comparing it to the libraries listed below

• ucsdsysnet / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆205Updated last year
• Xilinx / open-nic
  AMD OpenNIC Project Overview
  ☆301Updated 3 years ago
• KastnerRG / riffa
  The RIFFA development repository
  ☆863Updated last year
• fpgasystems / Vitis_with_100Gbps_TCP-IP
  100 Gbps TCP/IP stack for Vitis shells
  ☆228Updated last year
• corundum / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆2,200Updated last year
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,526Updated last year
• Xilinx / dma_ip_drivers
  Xilinx QDMA IP Drivers
  ☆761Updated 2 months ago
• fpgasystems / Coyote
  Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…
  ☆323Updated last week
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆858Updated 11 months ago
• hpcn-uam / Limago
  Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
  ☆134Updated 4 years ago
• Xilinx / Vitis_Accel_Examples
  Vitis_Accel_Examples
  ☆582Updated last month
• NetFPGA / netfpga
  NetFPGA 1G infrastructure and gateware
  ☆384Updated 6 years ago
• Xilinx / xup_vitis_network_example
  VNx: Vitis Network Examples
  ☆156Updated 5 months ago
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆285Updated last year
• lastweek / fpga_readings
  Recipe for FPGA cooking
  ☆311Updated last year
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆601Updated 3 weeks ago
• Xilinx / open-nic-shell
  AMD OpenNIC Shell includes the HDL source files
  ☆136Updated last year
• Xilinx / Vitis_Libraries
  Vitis Libraries
  ☆1,065Updated last month
• Xilinx / Vitis-HLS-Introductory-Examples
  ☆758Updated 2 weeks ago
• KastnerRG / pp4fpgas
  Parallel Programming for FPGAs -- An open-source high-level synthesis book
  ☆875Updated 3 weeks ago
• bperez77 / xilinx_axidma
  A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communicat…
  ☆529Updated 3 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,487Updated last week
• hpcn-uam / 100G-fpga-network-stack-core
  This repo contains the Limago code
  ☆90Updated 9 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆632Updated 9 months ago
• Xilinx / XRT
  Run Time for AIE and FPGA based platforms
  ☆648Updated this week
• enjoy-digital / litepcie
  Small footprint and configurable PCIe core
  ☆660Updated this week
• Xilinx / HLS_packet_processing
  ☆49Updated 6 years ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,952Updated 11 months ago
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆403Updated 4 months ago
• Xilinx / XilinxBoardStore
  ☆312Updated this week