Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
☆407Jun 13, 2026Updated this week
Alternatives and similar repositories for Coyote
Users that are interested in Coyote are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.☆170Mar 20, 2025Updated last year
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆104Jun 30, 2025Updated 11 months ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆930Apr 15, 2026Updated 2 months ago
- 100 Gbps TCP/IP stack for Vitis shells☆236Apr 23, 2024Updated 2 years ago
- ☆13Jun 20, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Open source FPGA-based NIC and platform for in-network compute☆2,358Jul 5, 2024Updated last year
- VNx: Vitis Network Examples☆160Aug 25, 2025Updated 9 months ago
- FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs [ATC 22]☆144Aug 17, 2023Updated 2 years ago
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆25Apr 27, 2023Updated 3 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17May 26, 2021Updated 5 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Apr 27, 2026Updated last month
- ☆36Jan 21, 2021Updated 5 years ago
- AMD OpenNIC Shell includes the HDL source files☆142Jan 2, 2025Updated last year
- AMD OpenNIC Project Overview☆328Dec 20, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Ensō is a high-performance streaming interface for NIC-application communication.☆80Apr 11, 2026Updated 2 months ago
- Our contribution to the AMD Open Hardware Contest: A ML-based Deep Packet Inspection for RDMA-networking on FPGAs☆13May 6, 2026Updated last month
- ETHZ Heterogeneous Accelerated Compute Cluster.☆41Updated this week
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆173Mar 12, 2026Updated 3 months ago
- ☆21Jan 31, 2026Updated 4 months ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆341Jan 20, 2025Updated last year
- Clio, ASPLOS'22.☆80Feb 8, 2022Updated 4 years ago
- AMD OpenNIC driver includes the Linux kernel driver☆76Jan 3, 2025Updated last year
- RPCNIC: A High-Performance and Reconfigurable PCIe-attached RPC Accelerator [HPCA2025]☆15Dec 9, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- The Task Parallel System Composer (TaPaSCo)☆126Updated this week
- Framework for FPGA-accelerated Middlebox Development☆49Feb 18, 2023Updated 3 years ago
- TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.☆56Jun 7, 2026Updated last week
- Vitis In-Depth Tutorials☆1,585May 22, 2026Updated 3 weeks ago
- ☆22Apr 2, 2023Updated 3 years ago
- A Programmable Hardware Architecture for Network Transport Logic☆37Oct 26, 2021Updated 4 years ago
- HLS-based Graph Processing Framework on FPGAs☆151Oct 11, 2022Updated 3 years ago
- Run Time for AIE and FPGA based platforms☆665Updated this week
- A curated list of awesome smartnic tutorials, papers and projects.☆299Oct 27, 2025Updated 7 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆108Sep 2, 2025Updated 9 months ago
- Distributed Accelerator OS☆68Apr 6, 2022Updated 4 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆385Jan 20, 2025Updated last year
- ☆61Oct 29, 2020Updated 5 years ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆138Sep 11, 2021Updated 4 years ago
- Vitis_Accel_Examples☆596Updated this week
- DPDK Drivers for AMD OpenNIC☆31Jul 20, 2023Updated 2 years ago