Alternatives and similar repositories for pyxir:

Users that are interested in pyxir are comparing it to the libraries listed below

• ucb-bar / onnxruntime-riscv
  Fork of upstream onnxruntime focused on supporting risc-v accelerators
  ☆83Updated last year
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated 2 years ago
• jgoeders / dac_sdc_2021
  ☆23Updated 3 years ago
• awai54st / LUTNet
  ☆56Updated 4 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆36Updated 4 years ago
• lukasc-ch / ExtendedBitPlaneCompression
  Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…
  ☆17Updated 5 years ago
• EECS-NTNU / bismo
  BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
  ☆132Updated 5 years ago
• Xilinx / finn-base
  Open Source Compiler Framework using ONNX as Frontend and IR
  ☆29Updated 2 years ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 5 years ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• StanfordAHA / Halide-to-Hardware
  ☆80Updated last week
• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆30Updated 5 years ago
• jgoeders / dac_sdc_2020
  DAC System Design Contest 2020
  ☆29Updated 4 years ago
• zeasa / nvdla-compiler
  ☆42Updated 5 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆60Updated 3 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆84Updated 4 months ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆25Updated 4 years ago
• Xilinx / logicnets
  ☆83Updated 8 months ago
• sfu-arch / SpGEMM
  ☆34Updated 3 years ago
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆36Updated 4 years ago
• DreamIP / haddoc2
  Caffe to VHDL
  ☆66Updated 4 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆55Updated 3 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 5 years ago
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆30Updated last year
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆78Updated 6 years ago
• tum-ei-eda / muriscv-nn
  muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.
  ☆69Updated 3 weeks ago
• TUD-ADS / HiFlipVX
  ☆17Updated 2 years ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆55Updated 6 months ago
• GATECH-EIC / AutoDNNchip
  ☆69Updated 4 years ago