Xilinx / pyxirLinks
☆37Updated 3 years ago
Alternatives and similar repositories for pyxir
Users that are interested in pyxir are comparing it to the libraries listed below
Sorting:
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆87Updated 2 years ago
- Open Source Compiler Framework using ONNX as Frontend and IR☆33Updated 3 years ago
- ☆60Updated 5 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated 2 years ago
- Train and deploy LUT-based neural networks on FPGAs☆99Updated last year
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆144Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 8 months ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- ☆85Updated 2 years ago
- ☆82Updated 8 months ago
- ☆23Updated 4 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆164Updated 3 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆30Updated 6 years ago
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆14Updated 2 years ago
- ☆72Updated 2 years ago
- A tool to deploy Deep Neural Networks on PULP-based SoC's☆88Updated 2 months ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- A DSL for Systolic Arrays☆82Updated 6 years ago
- ☆35Updated 6 years ago
- HLS branch of Halide☆79Updated 7 years ago
- ☆22Updated 3 years ago
- PyTorch model to RTL flow for low latency inference☆130Updated last year
- A polyhedral compiler for hardware accelerators☆59Updated last year
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆15Updated 9 months ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- Caffe to VHDL☆68Updated 5 years ago
- Systolic-array based Deep Learning Accelerator generator☆27Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago