Alternatives and similar repositories for pyxir

Users that are interested in pyxir are comparing it to the libraries listed below

• ucb-bar / onnxruntime-riscv
  Fork of upstream onnxruntime focused on supporting risc-v accelerators
  ☆88Updated 2 years ago
• EECS-NTNU / bismo
  BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
  ☆146Updated 5 years ago
• Xilinx / finn-base
  Open Source Compiler Framework using ONNX as Frontend and IR
  ☆33Updated 3 years ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆34Updated 2 years ago
• awai54st / LUTNet
  ☆61Updated 5 years ago
• jgoeders / dac_sdc_2021
  ☆23Updated 4 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆49Updated 8 months ago
• pulp-platform / pulp-nn
  ☆86Updated 2 years ago
• pulp-platform / dory
  A tool to deploy Deep Neural Networks on PULP-based SoC's
  ☆90Updated 3 months ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆101Updated last year
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆38Updated 5 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆35Updated 6 years ago
• CSL-KU / firesim-nvdla
  FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud
  ☆164Updated 3 years ago
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆33Updated 2 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• jgoeders / dac_sdc_2020
  DAC System Design Contest 2020
  ☆29Updated 5 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆59Updated 3 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆82Updated 6 years ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 5 years ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 6 years ago
• ARM-software / DeepFreeze
  ☆40Updated 5 years ago
• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆42Updated 5 years ago
• DreamIP / haddoc2
  Caffe to VHDL
  ☆68Updated 5 years ago
• zeasa / nvdla-compiler
  ☆46Updated 5 years ago
• heterosys / mlir-vitis
  📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.
  ☆14Updated 3 years ago
• jgoeders / dac_sdc_2021_designs
  ☆20Updated 3 years ago
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆130Updated last year
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆58Updated last month