gkrislara / Image-super-resolution-FPGALinks
Deployment of Deep learning Image Super-Resolution Models in Xilinx Zynq MPSoC ZCU102
☆16Updated 5 years ago
Alternatives and similar repositories for Image-super-resolution-FPGA
Users that are interested in Image-super-resolution-FPGA are comparing it to the libraries listed below
Sorting:
- ☆26Updated 2 years ago
- ☆20Updated 3 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Updated 5 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- ☆21Updated 2 years ago
- ☆17Updated 2 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆26Updated 3 years ago
- CNN accelerator implemented with Spinal HDL☆152Updated last year
- This project is to implement YOLO v3 on Xilinx FPGA with DPU☆63Updated 5 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 3 years ago
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆11Updated 5 years ago
- YOLO example implementation using Intuitus CNN accelerator on ZYBO ZYNQ-7000 FPGA board☆21Updated 4 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆38Updated 4 years ago
- ☆32Updated 4 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆20Updated 4 years ago
- 2020 xilinx summer school☆18Updated 5 years ago
- DMA controller for CNN accelerator☆14Updated 8 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆115Updated 4 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- This repository provides an FPGA-based solution for executing object detection, focusing specifically on the popular YOLOv5 model archite…☆48Updated 2 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Updated 2 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆99Updated last year
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆47Updated 5 years ago
- 在FPGA上部署深度学习项目☆22Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- This repository contains source code for CNN layers of ALexNet using Xilinx HLS Vivado.☆10Updated 3 years ago
- Lecture Material on Deep Learning Inference using FPGA☆12Updated 5 years ago