Alternatives and similar repositories for muSYCL:

Users that are interested in muSYCL are comparing it to the libraries listed below

• rehohoho / onnx2versal
  Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.
  ☆9Updated 3 weeks ago
• triSYCL / sycl
  SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
  ☆115Updated 2 months ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆55Updated 5 months ago
• spcl / SMI
  Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware
  ☆16Updated 2 years ago
• hpcgarage / spatter
  Benchmark for measuring the performance of sparse and irregular memory access.
  ☆76Updated this week
• stillwater-sc / hpr-blas
  High-Performance Reproducible BLAS using posit arithmetic
  ☆12Updated 2 years ago
• spcl / FBLAS
  BLAS implementation for Intel FPGA
  ☆76Updated 4 years ago
• David-Durst / embeddedHaskellAetherling
  ☆25Updated 2 years ago
• nod-ai / iree-amd-aie
  IREE plugin repository for the AMD AIE accelerator
  ☆72Updated this week
• andrewbartolo / accel-sim
  Accelerator simulation framework using nn_dataflow traces and energy, etc. post-processing
  ☆7Updated 5 years ago
• tobiasgrosser / islplot
  Library to plot integer sets and maps
  ☆48Updated 8 years ago
• template-hls / template-hls-float
  ☆27Updated 5 years ago
• maltanar / gemmbitserial
  Fast matrix multiplication for few-bit integer matrices on CPUs.
  ☆27Updated 5 years ago
• Huawei-CPLLab / SYCLops
  A SYCL-specific LLVM-to-MLIR converter
  ☆1Updated last year
• Xilinx / xacc
  Heterogeneous Accelerated Computed Cluster (HACC) Resources Page
  ☆20Updated last month
• UCSBarchlab / Charm
  A Language for Closed-form High-level ARchitecture Modeling
  ☆19Updated 4 years ago
• Xilinx / finn-base
  Open Source Compiler Framework using ONNX as Frontend and IR
  ☆29Updated 2 years ago
• stephenneuendorffer / vyasa
  Xilinx Modifications to Halide
  ☆12Updated 3 years ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆32Updated last year
• unisa-hpc / sycl-bench
  SYCL Benchmark Suite
  ☆60Updated 4 months ago
• ProGTX / sycl-gtx
  Implementation of the SYCL specification.
  ☆67Updated 7 months ago
• chai-benchmarks / chai
  Chai
  ☆42Updated last year
• parsa-epfl / HBFPEmulator
  ColTraIn HBFP Training Emulator
  ☆16Updated last year
• gthparch / NVPTX-SPIRV-Translator
  ☆20Updated 3 years ago
• owensgroup / gpustats
  Statistics on GPUs
  ☆29Updated 4 months ago
• ROCm / hipCollections
  Header-only library of GPU-accelerated, concurrent data structures.
  ☆10Updated last month
• esa-tu-darmstadt / spn-compiler
  Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.
  ☆23Updated last month
• necst / sdaccel_chisel_integration
  Chisel Project for Integrating RTL code into SDAccel
  ☆17Updated 7 years ago
• jingpu / Halide-HLS
  HLS branch of Halide
  ☆77Updated 6 years ago
• CMU-SAFARI / SPARTA
  A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…
  ☆18Updated last year