Alternatives and similar repositories for Getting-to-Know-Vivado

Users that are interested in Getting-to-Know-Vivado are comparing it to the libraries listed below

• FPGA-Research / fos
  FOS - FPGA Operating System
  ☆72Updated 4 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated 2 months ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆60Updated 2 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆90Updated 6 years ago
• louisliuwei / FPGA-Design-Flow-using-Vivado
  This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
  ☆40Updated 5 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆95Updated 4 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆58Updated last week
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆114Updated 2 weeks ago
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆66Updated 8 years ago
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆208Updated last year
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆67Updated 7 months ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆66Updated last week
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆85Updated 5 years ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆20Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• Essenceia / low-latency-ethernet
  RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.
  ☆44Updated last year
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆50Updated 2 years ago
• HDLForBeginners / Examples
  ☆106Updated 2 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆111Updated last year
• xupgit / FPGA-Design-Flow-using-Vivado
  This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
  ☆103Updated 5 years ago
• open-design / riscv-soc-cores
  ☆39Updated 4 years ago
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆30Updated last year
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆73Updated 3 weeks ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆65Updated 5 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆46Updated 11 years ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆78Updated this week
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆116Updated 4 years ago