Alternatives and similar repositories for qnn-inference-examples:

Users that are interested in qnn-inference-examples are comparing it to the libraries listed below

• Xilinx / finn-examples
  Dataflow QNN inference accelerator examples on FPGAs
  ☆213Updated last month
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆58Updated 3 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆192Updated last week
• Xilinx / LSTM-PYNQ
  ☆87Updated 5 years ago
• EECS-NTNU / bismo
  BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
  ☆137Updated 5 years ago
• QDucasse / nn_benchmark
  🧠 Benchmark facility to train networks on different datasets for PyTorch/Brevitas
  ☆25Updated 2 years ago
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆102Updated 2 years ago
• awai54st / LUTNet
  ☆57Updated 5 years ago
• Xilinx / RFNoC-HLS-NeuralNet
  ☆106Updated 5 years ago
• Xilinx / logicnets
  ☆91Updated 10 months ago
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆44Updated last year
• EEESlab / combinational-bnn
  System Verilog code describing a fully combinational binarized neural network.
  ☆33Updated 6 years ago
• thesps / conifer
  Fast inference of Boosted Decision Trees in FPGAs
  ☆53Updated last month
• Xilinx / QNN-MO-PYNQ
  ☆246Updated 4 years ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆32Updated last year
• Xilinx / PYNQ-BOT
  ☆28Updated 7 years ago
• Xilinx / finn-base
  Open Source Compiler Framework using ONNX as Frontend and IR
  ☆30Updated 2 years ago
• AlexMontgomerie / fpgaconvnet-hls
  ☆29Updated 5 months ago
• mohdumar644 / TinyYOLO-BNN
  Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.
  ☆30Updated 6 years ago
• heheda365 / ultra_net
  FPGA-based neural network inference project for 2020 DAC System Design Contest
  ☆112Updated 4 years ago
• hillhao / PYNQ-project
  PYNQ, Neural network Language model, Overlay
  ☆106Updated 6 years ago
• hsharma35 / dnnweaver2
  Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
  ☆212Updated 6 years ago
• ralbertazzi / bnn
  Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
  ☆50Updated 6 years ago
• hirayaku / DAC2018-TGIIF
  The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track
  ☆89Updated 6 years ago
• Yang-YiFan / DiracDeltaNet
  PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
  ☆31Updated 5 years ago
• onioncc / iSmartDNN
  Light-weighted neural network inference for object detection on small-scale FPGA board
  ☆91Updated 5 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆104Updated 7 years ago
• mohaghasemzadeh / ReBNet
  Residual Binarized Neural Network
  ☆43Updated 7 years ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆219Updated last year
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago