Alternatives and similar repositories for Read_the_docs:

Users that are interested in Read_the_docs are comparing it to the libraries listed below

• cathalmccabe / PYNQ_tutorials
  ☆73Updated last year
• snagiri / CSE237D-PYNQ-SNN-Accelerator
  Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board
  ☆32Updated 5 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆54Updated 3 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆34Updated 2 years ago
• sazczmh / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆37Updated 5 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆56Updated 5 months ago
• fastmachinelearning / models
  Models and examples built with hls4ml
  ☆12Updated 4 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆70Updated 7 months ago
• mohdumar644 / TinyYOLO-BNN
  Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.
  ☆31Updated 5 years ago
• sharc-lab / FPGA_ECE8893
  ☆33Updated this week
• manoharvhr / PYNQ-Torch
  PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform
  ☆68Updated 4 years ago
• briansune / PYNQ-2.7-MNIST
  PYNQ-Based MNIST with Tensorflow Lite
  ☆18Updated last year
• lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
  This project implements a convolution kernel based on vivado HLS on zcu104
  ☆36Updated 4 years ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆27Updated 4 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆189Updated last month
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 4 years ago
• FedericoSerafini / HLS-CNN
  High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
  ☆33Updated 6 months ago
• bol-edu / 2022-fall-ntu
  ☆28Updated 4 months ago
• DSDL-EE / PYNQ-ZU_Tutorial
  ☆12Updated last year
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• kaiiiz / hls-spmv
  High-level synthesis (HLS) implementation of Sparse Matrix Vector Multiplication
  ☆15Updated 2 years ago
• trung-pham-dinh / CNN-on-FPGA
  ☆16Updated 2 years ago
• UCLA-VAST / CLINK
  Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.
  ☆17Updated 5 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆84Updated 4 years ago
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆45Updated 4 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆60Updated 6 years ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆127Updated 2 weeks ago
• 0x5b25 / CNN_Core
  A CNN accelerator design inspired by MIT Eyeriss project
  ☆17Updated 3 years ago
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆27Updated last year
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆136Updated 5 years ago