Alternatives and similar repositories for spatial-multiverse:

Users that are interested in spatial-multiverse are comparing it to the libraries listed below

• da-steve101 / binary_connect_cifar
  An implementation of a BinaryConnect network for cifar10
  ☆11Updated 5 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆63Updated 3 years ago
• maeri-project / MAERI_bsv_isca2018
  MAERI public release
  ☆31Updated 3 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated last year
• cucapra / EventQueue
  EQueue Dialect
  ☆40Updated 3 years ago
• zhguanw / lin-analyzer
  A high-level performance analysis tool for FPGA-based accelerators
  ☆19Updated 7 years ago
• uwsampa / cse548-labs
  A repository containing homework labs for CSE548
  ☆40Updated 7 years ago
• StanfordAHA / aha
  ☆54Updated this week
• cornell-zhang / UniSparse
  Code base for OOPSLA'24 paper: UniSparse: An Intermediate Language for General Sparse Format Customization
  ☆30Updated 4 months ago
• template-hls / template-hls-float
  ☆27Updated 5 years ago
• PrincetonUniversity / accelerator-wall
  Repository for the tools and non-commercial data used for the "Accelerator wall" paper.
  ☆49Updated 6 years ago
• ARM-software / DeepFreeze
  ☆40Updated 5 years ago
• Blaok / tapa
  TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…
  ☆19Updated 6 months ago
• ucb-bar / onnxruntime-riscv
  Fork of upstream onnxruntime focused on supporting risc-v accelerators
  ☆83Updated last year
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• Xilinx / ACCL
  Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators
  ☆87Updated 4 months ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 2 years ago
• UCSBarchlab / Charm
  A Language for Closed-form High-level ARchitecture Modeling
  ☆20Updated 5 years ago
• twaclaw / matmult
  A floating-point matrix multiplication implemented in hardware
  ☆31Updated 4 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆68Updated 5 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆86Updated 5 months ago
• gopala-kr / DL-on-Silicon
  research, experimentation and implementation of hardware-agnostic accelerated DL framework
  ☆36Updated last month
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated 2 weeks ago
• hst10 / pylog
  PyLog: An Algorithm-Centric FPGA Programming and Synthesis Flow
  ☆64Updated last year
• Accelergy-Project / accelergy
  Accelergy is an energy estimation infrastructure for accelerator energy estimations
  ☆134Updated 2 weeks ago
• StanfordAHA / Halide-to-Hardware
  ☆80Updated last month
• cornell-zhang / hcl-dialect
  HeteroCL-MLIR dialect for accelerator design
  ☆41Updated 5 months ago
• esa-tu-darmstadt / spn-compiler
  Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.
  ☆23Updated 3 months ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆32Updated last year
• CMU-SAFARI / GPGPUSim-Ramulator
  The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…
  ☆50Updated 5 years ago