Alternatives and similar repositories for BinaryCoP

Users that are interested in BinaryCoP are comparing it to the libraries listed below

• union-codesign / union
  ☆14Updated 4 years ago
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 3 years ago
• ACADLab / SA-DS
  ☆13Updated last year
• ucb-bar / dosa
  DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators
  ☆18Updated last year
• cornell-zhang / allo-pldi24-artifact
  Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"
  ☆30Updated last year
• maestro-project / confuciux
  ☆32Updated 4 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆34Updated 2 years ago
• ttambe / AdaptivFloat
  Adaptive floating-point based numerical format for resilient deep learning
  ☆14Updated 3 years ago
• UCLA-VAST / heterohalide
  HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
  ☆15Updated 5 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆59Updated last month
• he-actlab / polymath
  ☆22Updated 9 months ago
• ucb-bar / MoCA
  ☆28Updated 2 years ago
• heterosys / mlir-vitis
  📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.
  ☆14Updated 3 years ago
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆30Updated 3 years ago
• GATECH-EIC / DNN-Chip-Predictor
  [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…
  ☆25Updated 3 years ago
• UCLA-VAST / splag
  Accelerating SSSP for power-law graphs using an FPGA.
  ☆23Updated 3 years ago
• ma3mool / goldeneye
  GoldenEye is a functional simulator with fault injection capabilities for common and emerging numerical formats, implemented for the PyTo…
  ☆26Updated last year
• Accelergy-Project / processing-in-memory-design
  ☆25Updated last year
• microideax / T-DLA
  ☆19Updated 5 years ago
• cornell-brg / torng-uecgra-scripts-hpca2021
  ☆11Updated 3 years ago
• priyanka-raina / dnn-accelerator
  ☆15Updated 5 years ago
• Xilinx / hydra
  ☆13Updated 3 years ago
• microideax / Open-Dnn
  ☆29Updated 6 years ago
• esa-tu-darmstadt / spn-compiler
  Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.
  ☆24Updated last year
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• enyac-group / MaxEVA
  MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)
  ☆22Updated last year
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• jgoeders / dac_sdc_2020
  DAC System Design Contest 2020
  ☆29Updated 5 years ago