Xilinx / SLASHLinks
A research shell for Alveo V80
☆13Updated last week
Alternatives and similar repositories for SLASH
Users that are interested in SLASH are comparing it to the libraries listed below
Sorting:
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆23Updated last month
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- ☆10Updated 2 years ago
- ☆24Updated 4 years ago
- ☆14Updated 2 years ago
- ☆55Updated 3 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆47Updated 2 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆92Updated 8 months ago
- Public repostory for the DAC 2021 paper "Scaling up HBM Efficiency of Top-K SpMV forApproximate Embedding Similarity on FPGAs"☆14Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆72Updated 6 years ago
- [FPGA 2024] Source code and bitstream for LevelST: Stream-based Accelerator for Sparse Triangular Solver☆12Updated 3 weeks ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆54Updated this week
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆22Updated 4 months ago
- ☆71Updated 2 years ago
- ☆30Updated 7 months ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- Processing in Memory Emulation☆20Updated 2 years ago
- DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators☆15Updated 8 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 8 months ago
- ☆11Updated 3 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆36Updated last month
- ☆13Updated 2 years ago
- Graph-learning assisted instruction vulnerability estimation published in DATE 2020☆14Updated 4 years ago
- ACM TODAES Best Paper Award, 2022☆25Updated last year
- ☆29Updated 6 years ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆38Updated last month
- ☆41Updated 11 months ago