Alternatives and similar repositories for logicnets

Users that are interested in logicnets are comparing it to the libraries listed below

• awai54st / LUTNet
  ☆58Updated 5 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆79Updated 2 weeks ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆58Updated 3 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• ehw-fit / evoapproxlib
  Library of approximate arithmetic circuits
  ☆53Updated 2 years ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• lana555 / dynamatic
  ☆86Updated last year
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• MartaAndronic / NeuraLUT
  NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions
  ☆32Updated 2 months ago
• awai54st / Logic-Shrinkage
  ☆23Updated 2 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆198Updated this week
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• template-hls / template-hls-float
  ☆29Updated 6 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆79Updated 10 months ago
• ARM-software / DeepFreeze
  ☆40Updated 5 years ago
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆45Updated last year
• ac-optimus / Convolution-using-systolic-arrays
  ☆65Updated 6 years ago
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆36Updated 2 weeks ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆143Updated this week
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆72Updated 11 months ago
• hyoukjun / OpenSMART
  Public release
  ☆51Updated 5 years ago
• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆28Updated 8 months ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 3 months ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆66Updated 2 years ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• rapidstream-org / rapidstream-tapa
  RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆170Updated this week
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆53Updated last month
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆52Updated 3 years ago