Alternatives and similar repositories for logicnets

Users that are interested in logicnets are comparing it to the libraries listed below

• awai54st / LUTNet
  ☆64Updated 5 years ago
• MartaAndronic / NeuraLUT
  NeuraLUT-Assemble
  ☆46Updated 4 months ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆100Updated last week
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆59Updated 4 years ago
• UCLA-VAST / tapa
  TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.
  ☆176Updated 4 months ago
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆83Updated 7 years ago
• AlexMontgomerie / fpgaconvnet-model
  Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
  ☆30Updated last year
• lana555 / dynamatic
  ☆87Updated last year
• VeriGOOD-ML / public
  ☆65Updated 7 months ago
• ehw-fit / evoapproxlib
  Library of approximate arithmetic circuits
  ☆61Updated 3 years ago
• awai54st / Logic-Shrinkage
  ☆22Updated 3 years ago
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)
  ☆169Updated 2 years ago
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆131Updated last year
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆210Updated last week
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆52Updated 2 years ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆149Updated this week
• MartaAndronic / PolyLUT
  PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…
  ☆56Updated last year
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆162Updated last week
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆127Updated 2 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆49Updated 9 months ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆73Updated this week
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆126Updated 3 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• ARM-software / DeepFreeze
  ☆40Updated 6 years ago
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆205Updated 5 years ago
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆38Updated 5 months ago
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆46Updated last year
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆204Updated 4 years ago