Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.
☆20Dec 29, 2024Updated last year
Alternatives and similar repositories for onnx2versal
Users that are interested in onnx2versal are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A compiler for lowering quantized ML models to optimized AMD AI Engine (AIE) firmware.☆25Updated this week
- ☆26Updated this week
- ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)☆68Mar 8, 2026Updated 7 months ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆22Apr 17, 2024Updated 2 years ago
- Reconfigurable Stream Network Architecture☆18Aug 13, 2026Updated 2 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆75Aug 1, 2025Updated last year
- Xilinx Modifications to Halide☆14May 3, 2021Updated 5 years ago
- muSYCL, the SYCL musical!☆13Aug 25, 2024Updated 2 years ago
- Chisel Project for Integrating RTL code into SDAccel☆17Jan 12, 2018Updated 8 years ago
- NPUEval is an LLM evaluation dataset written specifically to target AIE kernel code generation on RyzenAI hardware.☆34Nov 8, 2025Updated 11 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆178Mar 12, 2026Updated 7 months ago
- Legacy High Granularity Quantizarion 1 - Please use HGQ2 instead (https://github.com/calad0i/HGQ)☆40Mar 13, 2026Updated 7 months ago
- An accelerator to which you can offload RE matching☆14Dec 22, 2024Updated last year
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆23Jul 27, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- DFVG: A Heterogeneous Architecture for Speculative Decoding with Draft-on-FPGA and Verify-on-GPU.☆28Nov 26, 2025Updated 10 months ago
- An implementation of a BinaryConnect network for cifar10☆11Nov 4, 2019Updated 6 years ago
- A close-to-metal Python API for programming AMD Ryzen™ AI NPUs (AI Engines), built on an open-source MLIR-based compiler toolchain.☆702Updated this week
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆29May 18, 2025Updated last year
- Generate an FPGA design for a TWN☆11Nov 4, 2019Updated 6 years ago
- Fork of LLVM to support AMD AIEngine processors☆214Oct 9, 2026Updated last week
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆33Nov 13, 2023Updated 2 years ago
- Open-source AI acceleration on FPGA: from ONNX to RTL☆61Oct 9, 2026Updated last week
- Successfully training approximations to full-rank matrices for efficiency in deep learning.☆16Jan 5, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Classify modulation of signals☆16Jan 16, 2020Updated 6 years ago
- ☆25Sep 9, 2026Updated last month
- ☆64Mar 24, 2025Updated last year
- An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE☆17Aug 5, 2022Updated 4 years ago
- CODO: An Automated Compiler for Comprehensive Dataflow Optimization☆41Jun 3, 2026Updated 4 months ago
- Fast inference of Boosted Decision Trees in FPGAs☆64Oct 6, 2026Updated last week
- High-Performance Reproducible BLAS using posit arithmetic☆12Mar 16, 2022Updated 4 years ago
- Open Source Compiler Framework using ONNX as Frontend and IR☆33Aug 17, 2022Updated 4 years ago
- ☆28Oct 25, 2021Updated 4 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆38Mar 12, 2026Updated 7 months ago
- Distributed arithmetic optimization for quantized nn on FPGAs☆27Apr 15, 2026Updated 6 months ago
- GoldenEye is a functional simulator with fault injection capabilities for common and emerging numerical formats, implemented for the PyTo…☆27Oct 22, 2024Updated last year
- The VD100 development board is based on the Xilinx Versal AI Edge series chip xcve2302 and is designed with a core board and a bottom boa…☆21Jul 9, 2024Updated 2 years ago
- Ready-to-link, packaged Aurora IP on four QSFP28 lanes, providing 100Gb/s throughput, flow control and status monitoring☆19Sep 28, 2026Updated 2 weeks ago
- ☆10Jun 13, 2023Updated 3 years ago
- Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…☆20Jan 21, 2022Updated 4 years ago