shashank-agg / octorayLinks
☆10Updated 4 years ago
Alternatives and similar repositories for octoray
Users that are interested in octoray are comparing it to the libraries listed below
Sorting:
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- ☆30Updated 6 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Updated last month
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- ☆24Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆23Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- HLS project modeling various sparse accelerators.☆12Updated 3 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Algorithmic C Machine Learning Library☆26Updated 2 weeks ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆23Updated 4 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- ☆87Updated last year
- ☆64Updated 7 months ago
- ☆13Updated last year
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- Alveo Versal Example Design☆48Updated last week
- ☆72Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆22Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆72Updated 8 months ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 5 months ago
- ☆60Updated 2 years ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 6 years ago
- ☆17Updated 3 years ago
- Hybrid Threading Tool Set☆15Updated 5 years ago