Alternatives and similar repositories for octoray

Users that are interested in octoray are comparing it to the libraries listed below

• wincle626 / HLS_Legup
  ☆29Updated 8 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• sharc-lab / gnn-builder
  An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization
  ☆24Updated last year
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated 2 years ago
• Junyi-Liu / benchmarks-HLS
  Benchmarks, testbenches, and transformed codes for high-level synthesis research
  ☆13Updated 8 years ago
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆26Updated last month
• Xilinx / xacc
  Heterogeneous Accelerated Computed Cluster (HACC) Resources Page
  ☆22Updated 4 months ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆35Updated 8 months ago
• georgia-tech-synergy-lab / hardtaco-hls
  HLS project modeling various sparse accelerators.
  ☆12Updated 4 years ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆32Updated 2 years ago
• maltanar / spmvaccsim
  A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.
  ☆15Updated 11 years ago
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆52Updated 2 years ago
• UofT-HPRC / galapagos
  ☆15Updated 7 months ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆48Updated 3 weeks ago
• Blaok / tapa
  TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…
  ☆19Updated last year
• coleblackman / TIDENet
  TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…
  ☆17Updated 3 years ago
• icgrp / hipr
  ☆17Updated 3 years ago
• UCLA-VAST / splag
  Accelerating SSSP for power-law graphs using an FPGA.
  ☆23Updated 3 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• Xilinx / merlin-compiler
  ☆60Updated 2 years ago
• hyoukjun / microswitch-noc
  ☆29Updated 6 years ago
• UCLA-VAST / hbmbench
  ☆24Updated 5 years ago
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆34Updated 7 years ago
• TUD-ADS / HiFlipVX
  ☆19Updated 3 years ago
• VeriGOOD-ML / public
  ☆65Updated 9 months ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆43Updated last month
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆73Updated last month
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆30Updated 2 years ago