shashank-agg / octorayLinks
☆10Updated 4 years ago
Alternatives and similar repositories for octoray
Users that are interested in octoray are comparing it to the libraries listed below
Sorting:
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 9 months ago
- Tutorial for integrating PyMTL and Vivado HLS☆18Updated 9 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- Algorithmic C Machine Learning Library☆23Updated 5 months ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- Fast Floating Point Operators for High Level Synthesis☆21Updated 2 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 2 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- ☆29Updated 6 years ago
- ☆15Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated this week
- DUTH RISC V Microprocessor for High Level Synthesis☆10Updated last year
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆21Updated 3 weeks ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- ☆16Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 3 months ago
- A graph linear algebra overlay☆51Updated 2 years ago
- ☆21Updated 2 years ago
- ☆58Updated 5 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40Updated 3 years ago
- ☆12Updated 10 months ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- A Generic Distributed Auto-Tuning Infrastructure☆22Updated 3 years ago