shashank-agg / octorayLinks
☆10Updated 4 years ago
Alternatives and similar repositories for octoray
Users that are interested in octoray are comparing it to the libraries listed below
Sorting:
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆24Updated last year
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Updated 11 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆32Updated 2 years ago
- ☆24Updated 5 years ago
- ☆30Updated 6 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆65Updated 9 months ago
- CoMeT is a new low-cost RowHammer mitigation that uses Count-Min Sketch-based aggressor row tracking, as described in our HPCA'24 paper h…☆11Updated last week
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆48Updated 2 weeks ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- ☆87Updated last year
- ☆29Updated 6 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆27Updated 6 years ago
- Algorithmic C Machine Learning Library☆26Updated 3 weeks ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Updated 5 years ago
- ☆18Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆79Updated 2 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- HLS project modeling various sparse accelerators.☆12Updated 4 years ago
- ☆14Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- ☆15Updated 7 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆128Updated 3 years ago
- ☆33Updated 6 years ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year