Alternatives and similar repositories for octoray

Users that are interested in octoray are comparing it to the libraries listed below

• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆26Updated this week
• Junyi-Liu / benchmarks-HLS
  Benchmarks, testbenches, and transformed codes for high-level synthesis research
  ☆13Updated 8 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆52Updated 2 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• sharc-lab / gnn-builder
  An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization
  ☆23Updated last year
• Blaok / tapa
  TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…
  ☆19Updated last year
• hyoukjun / microswitch-noc
  ☆28Updated 6 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated 2 years ago
• estwings57 / HMC-MAC
  Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube
  ☆12Updated 8 years ago
• lana555 / dynamatic
  ☆87Updated last year
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆30Updated 2 years ago
• Xilinx / xacc
  Heterogeneous Accelerated Computed Cluster (HACC) Resources Page
  ☆22Updated 3 months ago
• VeriGOOD-ML / public
  ☆65Updated 8 months ago
• maltanar / spmvaccsim
  A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.
  ☆15Updated 11 years ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆34Updated 7 months ago
• ic-lab-duth / FusedGCN4HLS
  Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis
  ☆23Updated 3 years ago
• TonyBrewer / OpenHT
  Hybrid Threading Tool Set
  ☆15Updated 5 years ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆46Updated this week
• ic-lab-duth / DRIM4HLS
  DUTH RISC V Microprocessor for High Level Synthesis
  ☆10Updated 2 years ago
• wincle626 / HLS_Legup
  ☆29Updated 8 years ago
• linghaosong / Serpens
  An HBM FPGA based SpMV Accelerator
  ☆17Updated last year
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• UCLA-VAST / hbmbench
  ☆24Updated 5 years ago
• jasonlin316 / Systolic-Array-for-Smith-Waterman
  This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …
  ☆27Updated 6 years ago
• kiabuzz / CompressedLUT
  A tool to generate optimized hardware files for univariate functions.
  ☆29Updated last year
• georgia-tech-synergy-lab / hardtaco-hls
  HLS project modeling various sparse accelerators.
  ☆12Updated 4 years ago
• UCLA-VAST / splag
  Accelerating SSSP for power-law graphs using an FPGA.
  ☆23Updated 3 years ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 4 years ago