open-sdr / openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
☆3,872Updated this week
Related projects ⓘ
Alternatives and complementary repositories for openwifi
- open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware☆698Updated 11 months ago
- Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.☆375Updated last year
- bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem☆391Updated 6 months ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,115Updated 3 weeks ago
- 基于ZYNQ+AD9363的开源SDR硬件☆420Updated 2 years ago
- The USRP™ Hardware Driver Repository☆995Updated this week
- Open source FPGA-based NIC and platform for in-network compute☆1,703Updated 4 months ago
- Send video/audio over HDMI on an FPGA☆1,091Updated 9 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,505Updated 2 weeks ago
- Open source SDR 4G software suite from Software Radio Systems (SRS) https://docs.srsran.com/projects/4g☆3,478Updated 4 months ago
- Build your hardware, easily!☆2,992Updated this week
- IEEE 802.11 a/g/p Transceiver☆751Updated 2 months ago
- A small, light weight, RISC CPU soft core☆1,300Updated 3 weeks ago
- Bluetooth Low Energy (BLE) packet sniffer and transmitter for both standard and non standard (raw bit) based on Software Defined Radio (S…☆733Updated this week
- HDL libraries and projects☆1,523Updated this week
- Yosys Open SYnthesis Suite☆3,487Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆2,543Updated this week
- Rocket Chip Generator☆3,251Updated last week
- A modern hardware definition language and toolchain based on Python☆1,570Updated 3 weeks ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,136Updated 4 months ago
- Scots Army Knife for electronics☆1,920Updated this week
- Icarus Verilog☆2,853Updated last week
- Must-have verilog systemverilog modules☆1,649Updated this week
- Scala based HDL☆1,663Updated this week
- The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux☆2,278Updated this week
- Chisel: A Modern Hardware Design Language☆3,983Updated this week
- The RIFFA development repository☆774Updated 4 months ago
- nextpnr portable FPGA place and route tool☆1,305Updated 2 weeks ago
- Linux kernel variant from Analog Devices; see README.md for details☆446Updated this week
- Free open source Wi-Fi project☆19Updated 11 months ago