baloneymath / AncstrGNNLinks
☆18Updated 4 years ago
Alternatives and similar repositories for AncstrGNN
Users that are interested in AncstrGNN are comparing it to the libraries listed below
Sorting:
- Analog Placement Quality Prediction☆25Updated 2 years ago
- Artificial Netlist Generator☆45Updated last year
- just checking☆19Updated 3 years ago
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆85Updated last year
- Analog IC symmetry extraction benchmark of AncstrGNN☆10Updated last year
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆15Updated 2 years ago
- ☆17Updated 3 years ago
- Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.☆71Updated 5 months ago
- ☆69Updated last month
- Machine Generated Analog IC Layout☆262Updated last year
- ☆32Updated 2 years ago
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆54Updated last year
- Analog and mixed-signal automatic placer☆12Updated 2 years ago
- the awesome work, project and lab of EDA (Electronic Design Automation). continue update...☆24Updated last year
- ☆32Updated 4 years ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆141Updated 4 months ago
- ☆30Updated 2 years ago
- Circuit release of the MAGICAL project☆40Updated 5 years ago
- ☆24Updated last year
- ☆17Updated last year
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.☆33Updated 2 years ago
- ChiPBench:Benchmarking End-to-End Performance of AI-based Chip Placement Algorithms☆46Updated 2 months ago
- REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)☆59Updated 3 years ago
- GNN-RE datasets for circuit recognition☆55Updated 2 years ago
- ☆58Updated 4 years ago
- awesome-Analog-IC-Design-Automation☆44Updated 2 years ago
- This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024☆53Updated 11 months ago
- A project to perform the VLSI Physical Design Flow steps of partitioning, floorplan, placement and routing.☆13Updated 4 years ago
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.☆22Updated last year
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆59Updated 6 months ago