Alternatives and similar repositories for ActiveN:

Users that are interested in ActiveN are comparing it to the libraries listed below

• heterosys / mlir-vitis
  📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.
  ☆13Updated 2 years ago
• ucb-bar / RoSE
  A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…
  ☆41Updated 2 months ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆30Updated 11 months ago
• shieldforever / NeuronQuant
  [ASP-DAC 2025] "NeuronQuant: Accurate and Efficient Post-Training Quantization for Spiking Neural Networks" Official Implementation
  ☆10Updated 3 weeks ago
• cornell-zhang / hcl-dialect
  HeteroCL-MLIR dialect for accelerator design
  ☆40Updated 6 months ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• SNU-HPCS / NeuroSync
  NeuroSync: A Scalable and Accurate Brain Simulation System using Safe and Efficient Speculation (HPCA 2022)
  ☆10Updated 2 years ago
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆32Updated last year
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆26Updated 2 months ago
• YutaPic / FPU
  For CPU experiment
  ☆9Updated 4 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆38Updated 8 months ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆41Updated last month
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆26Updated last week
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• yonseicasl / NPUsim
  NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators
  ☆31Updated 3 months ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 4 months ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆18Updated 2 weeks ago
• amin-norollah / PAT-Noxim
  cycle accurate Network-on-Chip Simulator
  ☆27Updated last year
• THU-DSP-LAB / ventus-gpgpu-isa-simulator
  Ventus GPGPU ISA Simulator Based on Spike
  ☆42Updated last month
• RalphMao / EIE-simulator
  C++ RTL simulator for EIE(https://arxiv.org/abs/1602.01528)
  ☆22Updated 4 years ago
• horizon-research / CamJ
  CamJ: an energy modeling and system-level exploration framework for in-sensor visual computing
  ☆23Updated last year
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆39Updated 2 weeks ago
• RuokaiYin / LoAS
  LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks, MICRO 2024.
  ☆10Updated 2 weeks ago
• esa-tu-darmstadt / SCAIE-V
  An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:
  ☆14Updated last year
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆51Updated 3 years ago
• arc-research-lab / AIM
  AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…
  ☆22Updated this week
• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 3 years ago
• KULeuven-MICAS / zigzag-imc
  HW accelerator mapping optimization framework for in-memory computing
  ☆22Updated 2 months ago
• cornell-zhang / allo-pldi24-artifact
  Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"
  ☆22Updated 11 months ago