Alternatives and similar repositories for ActiveN

Users that are interested in ActiveN are comparing it to the libraries listed below

• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆13Updated last year
• heterosys / mlir-vitis
  📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.
  ☆15Updated 3 years ago
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆46Updated last week
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆45Updated last year
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆37Updated 2 months ago
• cornell-zhang / hcl-dialect
  HeteroCL-MLIR dialect for accelerator design
  ☆42Updated last year
• ucb-bar / AuRORA
  Virtualized Accelerator Orchestration for Multi-Tenant Workloads
  ☆19Updated last year
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆36Updated last year
• pku-liang / Hestia
  ☆17Updated 10 months ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆10Updated last week
• Synthesys-Lab / assassyn
  Asynchronous semantics for architectural simulation and synthesis.
  ☆65Updated 2 weeks ago
• arc-research-lab / Aries
  ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)
  ☆57Updated this week
• ucb-bar / RoSE
  A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…
  ☆45Updated 10 months ago
• YutaPic / FPU
  For CPU experiment
  ☆14Updated 4 years ago
• pulp-platform / redmule
  ☆90Updated this week
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 3 months ago
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆49Updated 6 months ago
• RalphMao / EIE-simulator
  C++ RTL simulator for EIE(https://arxiv.org/abs/1602.01528)
  ☆23Updated 4 years ago
• microsoft / brainsmith
  Open-source AI acceleration on FPGA: from ONNX to RTL
  ☆48Updated last month
• WangXuan95 / LLMA
  LLMA = LLM + Arithmetic coder, which use LLM to do insane text data compression. LLMA=大模型+算术编码，它能使用LLM对文本数据进行暴力的压缩，达到极高的压缩率。
  ☆22Updated last year
• pku-liang / ksim
  ☆52Updated last year
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆65Updated last year
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆118Updated 2 years ago
• THU-DSP-LAB / llvm-project
  LLVM OpenCL C compiler suite for ventus GPGPU
  ☆58Updated last month
• FPSG-UIUC / micro24-fusemax-artifact
  MICRO 2024 Evaluation Artifact for FuseMax
  ☆16Updated last year
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆64Updated 7 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆93Updated 2 months ago