☆41Jul 12, 2025Updated last year
Alternatives and similar repositories for mcp4eda
Users that are interested in mcp4eda are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This is the Github Repo for the paper: MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis O…☆105Jul 29, 2025Updated last year
- ☆15Jul 25, 2024Updated 2 years ago
- Dataset for ML-guided Accelerator Design☆45Nov 18, 2024Updated last year
- ☆16Mar 23, 2026Updated 4 months ago
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Contract-Aware RTL Code Generation Agents with Temporal Tracing, Slicing and Formal Verification☆24Jan 28, 2026Updated 6 months ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Aug 25, 2021Updated 4 years ago
- Netlist API (and more) for EDA flow development☆159Updated this week
- PROTON - A Python Framework for Physics-Based Electromigration Assessment on Contemporary VLSI Power Grids☆19Sep 10, 2024Updated last year
- Datasets for EDA LLM research☆46Jan 17, 2025Updated last year
- ☆18Feb 25, 2026Updated 5 months ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 8 months ago
- Project Status: Discontinued, New repository: spec2rtl-plugin☆30Feb 1, 2026Updated 6 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- The first large scale formally verified reasoning dataset for Verilog☆22May 16, 2025Updated last year
- 2d laser scan data to 3d point cloud☆11Feb 10, 2022Updated 4 years ago
- [DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers☆44Jul 9, 2025Updated last year
- ☆206Jun 8, 2026Updated 2 months ago
- PlutoSDR PYNQ Image☆16Aug 14, 2024Updated 2 years ago
- ☆17Jul 10, 2025Updated last year
- LLM4HWDesign Starting Toolkit☆20Oct 4, 2024Updated last year
- An experimental package manager and development tool for Hardware Description Languages (HDL).☆14Apr 10, 2022Updated 4 years ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Aug 25, 2024Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆16Jun 30, 2024Updated 2 years ago
- ☆13Oct 11, 2024Updated last year
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆35Apr 13, 2021Updated 5 years ago
- 64QAM Wireless communication on ADALM-PLUTO (a SDR active learning module), written in MATLAB, based on some APIs and existing functions.☆18Jul 4, 2023Updated 3 years ago
- ☆43Nov 28, 2022Updated 3 years ago
- LLM-aided Hardware Design and Verification☆38May 11, 2026Updated 3 months ago
- ☆116Jun 22, 2026Updated last month
- ☆113Dec 5, 2019Updated 6 years ago
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆42May 17, 2024Updated 2 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- System for verifying the correctness of generated Copilot programs☆19May 8, 2025Updated last year
- Source code for 'wxPython Recipes' by Mike Driscoll☆11Dec 4, 2017Updated 8 years ago
- 简洁的测试平台日志,波形(FSDB/VCD),根因分析MCP Server. A Simple and Universal MCP Server to Debug Testbench Simulation Failures Via Log Parsing And Wave…☆62Jul 30, 2026Updated 2 weeks ago
- ☆60Mar 10, 2025Updated last year
- This github repository summarizes relevant papers for shift left techniques in electronic design automation (EDA).☆34Jun 17, 2026Updated 2 months ago
- A RISC-V Core (RV32I) written in Chisel HDL☆108Aug 3, 2026Updated 2 weeks ago
- TBD☆15Feb 6, 2025Updated last year