Alternatives and similar repositories for SA-DS

Users that are interested in SA-DS are comparing it to the libraries listed below

• GATECH-EIC / Auto-NBA
  [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…
  ☆16Updated 4 years ago
• NaelF / BinaryCoP
  Binary Neural Network-based COVID-19 Face-Mask Wear and Positioning Predictor on Edge Devices
  ☆12Updated 4 years ago
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆22Updated 3 years ago
• GATECH-EIC / DNN-Chip-Predictor
  [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…
  ☆25Updated 3 years ago
• maestro-project / AIrchitect-v2
  [DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Represen…
  ☆19Updated last year
• GATECH-EIC / mg-verilog
  ☆54Updated last year
• harvard-acc / EdgeBERT
  HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference
  ☆54Updated last year
• GATECH-EIC / torchshiftadd
  An open-sourced PyTorch library for developing energy efficient multiplication-less models and applications.
  ☆14Updated last year
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• UCLA-VAST / heterohalide
  HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
  ☆15Updated 5 years ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated 2 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆62Updated 3 months ago
• ttambe / AdaptivFloat
  Adaptive floating-point based numerical format for resilient deep learning
  ☆14Updated 3 years ago
• lukasc-ch / ExtendedBitPlaneCompression
  Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…
  ☆19Updated 6 years ago
• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆58Updated last year
• priyanka-raina / dnn-accelerator
  ☆15Updated 5 years ago
• sfu-arch / SpGEMM
  ☆36Updated 4 years ago
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆32Updated 2 years ago
• GATECH-EIC / LLM4HWDesign_Starting_Toolkit
  LLM4HWDesign Starting Toolkit
  ☆19Updated last year
• Accelergy-Project / processing-in-memory-design
  ☆25Updated last year
• union-codesign / union
  ☆14Updated 4 years ago
• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 4 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆30Updated 2 years ago
• cornell-brg / torng-uecgra-scripts-hpca2021
  ☆11Updated 3 years ago
• ic-lab-duth / DRIM4HLS
  DUTH RISC V Microprocessor for High Level Synthesis
  ☆10Updated 2 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• fffasttime / AnyPackingNet
  ☆32Updated 10 months ago
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆30Updated 4 years ago
• ucb-bar / MoCA
  ☆28Updated 2 years ago
• rval735 / bisunaU50
  BiSUNA framework specialized to compile for the Xilinx Alveo U50
  ☆13Updated 5 years ago