ACADLab / SA-DSLinks
☆13Updated last year
Alternatives and similar repositories for SA-DS
Users that are interested in SA-DS are comparing it to the libraries listed below
Sorting:
- [DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Represen…☆17Updated 9 months ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 3 years ago
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆15Updated 3 years ago
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆52Updated last year
- Binary Neural Network-based COVID-19 Face-Mask Wear and Positioning Predictor on Edge Devices☆12Updated 4 years ago
- ☆15Updated 5 years ago
- ☆48Updated last year
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- ACM TODAES Best Paper Award, 2022☆28Updated last year
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 6 years ago
- ☆25Updated last year
- ☆14Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Adaptive floating-point based numerical format for resilient deep learning☆14Updated 3 years ago
- ☆35Updated 5 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆58Updated 2 weeks ago
- Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators☆11Updated 6 years ago
- ☆71Updated 5 years ago
- An open-sourced PyTorch library for developing energy efficient multiplication-less models and applications.☆13Updated 8 months ago
- ☆41Updated last year
- A general framework for optimizing DNN dataflow on systolic array☆38Updated 4 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 4 years ago
- A Toy-Purpose TPU Simulator☆19Updated last year
- ☆36Updated 4 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated 2 years ago
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆50Updated 10 months ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 5 years ago
- ☆22Updated 8 months ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆106Updated last year
- A DAG processor and compiler for a tree-based spatial datapath.☆14Updated 3 years ago