DARClab-UTD / S2CBenchLinks
☆15Updated 6 years ago
Alternatives and similar repositories for S2CBench
Users that are interested in S2CBench are comparing it to the libraries listed below
Sorting:
- Dataset for ML-guided Accelerator Design☆37Updated 8 months ago
- ☆43Updated 10 months ago
- An integrated CGRA design framework☆90Updated 4 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- The open-sourced version of BOOM-Explorer☆43Updated 2 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 2 weeks ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆51Updated 8 years ago
- Library of approximate arithmetic circuits☆55Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- DASS HLS Compiler☆29Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆128Updated 5 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆166Updated last year
- A list of our chiplet simulaters☆33Updated last month
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆135Updated last month
- Public release☆57Updated 5 years ago
- ☆62Updated 3 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆51Updated 2 months ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆30Updated 10 months ago
- CATCH 1.0, Initial full release of CATCH cost model.☆15Updated 2 weeks ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆18Updated 3 years ago
- ☆87Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆67Updated 4 months ago
- Project repo for the POSH on-chip network generator☆49Updated 4 months ago
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆18Updated 9 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Updated 6 years ago
- ☆77Updated 10 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆173Updated this week