Alternatives and similar repositories for S2CBench:

Users that are interested in S2CBench are comparing it to the libraries listed below

• pku-dasys / pillars
  An integrated CGRA design framework
  ☆87Updated last week
• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆22Updated 6 months ago
• hyoukjun / OpenSMART
  Public release
  ☆50Updated 5 years ago
• vaughnbetz / COFFE
  ☆41Updated 6 months ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆60Updated 2 months ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆36Updated 4 months ago
• hyoukjun / microswitch-noc
  ☆26Updated 5 years ago
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆14Updated 2 years ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆120Updated 4 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆49Updated 7 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆60Updated 5 years ago
• baichen318 / boom-explorer-public
  The open-sourced version of BOOM-Explorer
  ☆38Updated last year
• ecolab-nus / morpher-v2
  An Open-Source Tool for CGRA Accelerators
  ☆19Updated 11 months ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆33Updated 4 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆70Updated 3 years ago
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆33Updated last week
• tancheng / CGRA-Bench
  ☆14Updated 2 years ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆28Updated last week
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆24Updated last year
• lana555 / dynamatic
  ☆86Updated last year
• Davxx / gem5_Garnet2.0_extensions
  Fork of the gem5 simulator with Garnet2.0 and DSENT extensions
  ☆10Updated 6 years ago
• Xilinx / merlin-compiler
  ☆57Updated last year
• esl-epfl / HEEPsilon
  A low power platform based on X-HEEP and integrating the ESL-CGRA
  ☆13Updated 5 months ago
• chipsalliance / aib-protocols
  ☆25Updated last year
• ehw-fit / evoapproxlib
  Library of approximate arithmetic circuits
  ☆54Updated 2 years ago
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆71Updated 10 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆52Updated last week