DARClab-UTD / S2CBenchLinks
☆17Updated 6 years ago
Alternatives and similar repositories for S2CBench
Users that are interested in S2CBench are comparing it to the libraries listed below
Sorting:
- An integrated CGRA design framework☆91Updated 7 months ago
- ☆44Updated last year
- Dataset for ML-guided Accelerator Design☆39Updated 11 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆140Updated 4 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆53Updated 8 years ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆130Updated 5 years ago
- ☆87Updated last year
- A list of our chiplet simulaters☆43Updated 4 months ago
- An Open-Source Tool for CGRA Accelerators☆74Updated last month
- An Open-Source Tool for CGRA Accelerators☆25Updated last month
- Public release☆57Updated 6 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- The open-sourced version of BOOM-Explorer☆44Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆126Updated 2 years ago
- Project repo for the POSH on-chip network generator☆51Updated 7 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆35Updated last year
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 3 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- CGRA Compilation Framework☆88Updated 2 years ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆18Updated 3 years ago
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆18Updated 9 years ago
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆15Updated last month
- Library of approximate arithmetic circuits☆56Updated 3 years ago
- Collection of digital hardware modules & projects (benchmarks)☆65Updated last week
- A fast, accurate trace-based simulator for High-Level Synthesis.☆70Updated 7 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆58Updated 5 months ago