cornell-zhang / quickest
QuickEst repository: Quick Estimation of Quality of Results
☆26Updated 6 years ago
Alternatives and similar repositories for quickest:
Users that are interested in quickest are comparing it to the libraries listed below
- A Generic Distributed Auto-Tuning Infrastructure☆21Updated 3 years ago
- ☆11Updated 3 years ago
- ☆71Updated last year
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆89Updated 3 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆17Updated 5 months ago
- Graph-learning assisted instruction vulnerability estimation published in DATE 2020☆13Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- A graph linear algebra overlay☆50Updated last year
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- ☆37Updated 6 months ago
- Docker container with tools for the Timeloop/Accelergy tutorial☆22Updated 9 months ago
- ☆31Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆60Updated 3 years ago
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆47Updated 7 months ago
- ☆40Updated 10 months ago
- ☆16Updated last year
- ☆69Updated 4 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆84Updated 3 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆39Updated 8 months ago
- ☆9Updated last year
- ACM TODAES Best Paper Award, 2022☆24Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆47Updated this week
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆68Updated 2 years ago
- Simulator for BitFusion☆94Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆67Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆41Updated 2 years ago
- RTL implementation of Flex-DPE.☆97Updated 4 years ago
- DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators☆13Updated 3 months ago
- Template-based Reconfigurable Architecture Modeling Framework☆13Updated 2 years ago
- An end-to-end GCN inference accelerator written in HLS☆19Updated 2 years ago