cornell-zhang / quickestLinks
QuickEst repository: Quick Estimation of Quality of Results
☆26Updated 7 years ago
Alternatives and similar repositories for quickest
Users that are interested in quickest are comparing it to the libraries listed below
Sorting:
- A Generic Distributed Auto-Tuning Infrastructure☆22Updated 4 years ago
- ☆11Updated 4 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 4 years ago
- ☆72Updated 2 years ago
- ☆10Updated 2 years ago
- Tool for optimize CNN blocking☆93Updated 5 years ago
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆51Updated last year
- RTL implementation of Flex-DPE.☆113Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- ☆41Updated last year
- Graph-learning assisted instruction vulnerability estimation published in DATE 2020☆14Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆87Updated last year
- This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…☆44Updated 3 months ago
- ☆71Updated 5 years ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆70Updated 7 months ago
- ☆10Updated 6 years ago
- ☆32Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆35Updated 5 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆58Updated 2 weeks ago
- Simulator for BitFusion☆102Updated 5 years ago
- ☆60Updated 7 months ago
- A graph linear algebra overlay☆51Updated 2 years ago
- A Fast DNN Accelerator Design Space Exploration Framework.☆46Updated 3 years ago
- ACM TODAES Best Paper Award, 2022☆30Updated 2 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- MAERI public release☆31Updated 4 years ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆32Updated 6 years ago