☆61Mar 24, 2025Updated last year
Alternatives and similar repositories for ScaleHLS-HIDA
Users that are interested in ScaleHLS-HIDA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆64Aug 1, 2025Updated 8 months ago
- Allo Accelerator Design and Programming Framework (PLDI'24)☆369Mar 13, 2026Updated 3 weeks ago
- A scalable High-Level Synthesis framework on MLIR☆294May 15, 2024Updated last year
- ☆13Aug 1, 2024Updated last year
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆20Dec 10, 2024Updated last year
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- EQueue Dialect☆42Feb 3, 2022Updated 4 years ago
- An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE☆17Aug 5, 2022Updated 3 years ago
- FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository☆14Mar 13, 2025Updated last year
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆22Oct 31, 2024Updated last year
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆17Dec 29, 2024Updated last year
- ☆17Aug 29, 2024Updated last year
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆54Jun 6, 2024Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆74Dec 19, 2025Updated 3 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆65Oct 9, 2024Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆22Jul 27, 2023Updated 2 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆169Mar 12, 2026Updated 3 weeks ago
- UniSparse: An Intermediate Language for General Sparse Format Customization (OOPSLA'24)☆33Nov 12, 2024Updated last year
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆15Nov 15, 2022Updated 3 years ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆177Updated this week
- ☆51Dec 10, 2024Updated last year
- ☆13Apr 15, 2025Updated 11 months ago
- ☆131Updated this week
- SAMO: Streaming Architecture Mapping Optimisation☆35Oct 4, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆18Nov 12, 2025Updated 4 months ago
- Xilinx Modifications to Halide☆13May 3, 2021Updated 4 years ago
- [DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Represen…☆19Jan 17, 2025Updated last year
- Release of stream-specialization software/hardware stack.☆122May 5, 2023Updated 2 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆73Sep 29, 2025Updated 6 months ago
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆24May 23, 2024Updated last year
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆33Apr 11, 2024Updated last year
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆54Jul 17, 2023Updated 2 years ago
- OpenMP front-end based on LLVM for CGRAs☆10Oct 2, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- HeteroCL-MLIR dialect for accelerator design☆42Sep 18, 2024Updated last year
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆379Jan 20, 2025Updated last year
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Mar 17, 2022Updated 4 years ago
- TileFlow is a performance analysis tool based on Timeloop for fusion dataflows☆67Apr 12, 2024Updated last year
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Sep 14, 2020Updated 5 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆170Nov 7, 2023Updated 2 years ago
- ☆62Aug 4, 2023Updated 2 years ago