xcw-1010 / HLSPilotLinks
☆44Updated 11 months ago
Alternatives and similar repositories for HLSPilot
Users that are interested in HLSPilot are comparing it to the libraries listed below
Sorting:
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆102Updated 6 months ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆81Updated 8 months ago
- ☆49Updated 3 months ago
- ☆60Updated 7 months ago
- A list of our chiplet simulaters☆44Updated 4 months ago
- A co-design architecture on sparse attention☆54Updated 4 years ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆76Updated 6 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆48Updated last year
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆43Updated 3 months ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"☆47Updated 2 months ago
- Serpens is an HBM FPGA accelerator for SpMV☆22Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- ☆107Updated last year
- An Open-Source Tool for CGRA Accelerators☆76Updated 2 months ago
- ☆58Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆72Updated last year
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆69Updated last month
- ☆48Updated 5 months ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆68Updated 2 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆41Updated 2 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆30Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆70Updated 2 weeks ago
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆87Updated last year
- FSA: Fusing FlashAttention within a Single Systolic Array☆62Updated 3 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 4 months ago
- ☆32Updated last year
- The open-sourced version of BOOM-Explorer☆46Updated 2 years ago