stephenneuendorffer / vyasa
Xilinx Modifications to Halide
☆9Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for vyasa
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 2 months ago
- Polyhedral High-Level Synthesis in MLIR☆29Updated last year
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆23Updated this week
- A Language for Closed-form High-level ARchitecture Modeling☆19Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆19Updated this week
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆36Updated this week
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆57Updated 2 years ago
- Stencil with Optimized Dataflow Architecture☆15Updated 8 months ago
- ☆23Updated 4 years ago
- Floating point modules for CHISEL☆28Updated 10 years ago
- HeteroCL-MLIR dialect for accelerator design☆40Updated 2 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆44Updated last year
- FPGA acceleration of arbitrary precision floating point computations.☆37Updated 2 years ago
- A polyhedral compiler for hardware accelerators☆56Updated 3 months ago
- ☆10Updated 2 years ago
- A hardware synthesis framework with multi-level paradigm☆37Updated last year
- ☆13Updated last year
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆13Updated 2 years ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆29Updated 6 months ago
- DASS HLS Compiler☆27Updated last year
- ☆27Updated 5 years ago
- EQueue Dialect☆39Updated 2 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆16Updated 4 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆53Updated last month
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- ☆57Updated last year
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆70Updated last year
- A high-level performance analysis tool for FPGA-based accelerators☆18Updated 7 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 3 years ago