Alternatives and similar repositories for vyasa

Users that are interested in vyasa are comparing it to the libraries listed below

• hanchenye / polyaie
  An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE
  ☆17Updated 3 years ago
• kumasento / polsca
  Polyhedral High-Level Synthesis in MLIR
  ☆34Updated 2 years ago
• esa-tu-darmstadt / spn-compiler
  Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.
  ☆25Updated last year
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆64Updated last year
• Xilinx / merlin-compiler
  ☆60Updated 2 years ago
• Xilinx / aie-rt
  ☆23Updated last week
• cucapra / EventQueue
  EQueue Dialect
  ☆41Updated 3 years ago
• cornell-zhang / hcl-dialect
  HeteroCL-MLIR dialect for accelerator design
  ☆42Updated last year
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆59Updated last year
• Xilinx / ACCL
  Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators
  ☆98Updated 6 months ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆79Updated 2 weeks ago
• StanfordAHA / aha
  ☆62Updated 2 weeks ago
• rehohoho / onnx2versal
  Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.
  ☆15Updated last year
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆53Updated 2 years ago
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆43Updated 11 months ago
• TeCSAR-UNCC / gem5-SALAM
  ☆108Updated last year
• CMU-SAFARI / SPARTA
  A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…
  ☆22Updated 2 years ago
• lana555 / dynamatic
  ☆87Updated last year
• UCLA-VAST / soda-compiler
  Stencil with Optimized Dataflow Architecture Compiler
  ☆17Updated 5 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆43Updated 6 months ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated 2 years ago
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆89Updated 2 years ago
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆61Updated 9 months ago
• Xilinx / mlir-air
  ☆121Updated last week
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆73Updated last week
• Xilinx / mlir-xten
  ☆16Updated this week
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆135Updated 5 years ago
• hst10 / pylog
  PyLog: An Algorithm-Centric FPGA Programming and Synthesis Flow
  ☆69Updated 2 years ago
• PrincetonUniversity / accelerator-wall
  Repository for the tools and non-commercial data used for the "Accelerator wall" paper.
  ☆52Updated 6 years ago