stephenneuendorffer / vyasaLinks
Xilinx Modifications to Halide
☆13Updated 4 years ago
Alternatives and similar repositories for vyasa
Users that are interested in vyasa are comparing it to the libraries listed below
Sorting:
- ☆103Updated last week
- A polyhedral compiler for hardware accelerators☆59Updated last year
- Polyhedral High-Level Synthesis in MLIR☆33Updated 2 years ago
- A hardware synthesis framework with multi-level paradigm☆40Updated 6 months ago
- ☆58Updated 2 years ago
- EQueue Dialect☆40Updated 3 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆50Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆60Updated 9 months ago
- ☆24Updated 4 years ago
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆14Updated 7 months ago
- ☆92Updated last year
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆24Updated 8 months ago
- ☆59Updated this week
- ☆56Updated 4 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆128Updated 5 years ago
- ☆30Updated 6 years ago
- HeteroCL-MLIR dialect for accelerator design☆41Updated 10 months ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆98Updated last month
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆21Updated last year
- Stencil with Optimized Dataflow Architecture Compiler☆17Updated 5 years ago
- ☆20Updated 2 weeks ago
- ☆86Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆76Updated 6 years ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆51Updated 6 years ago
- DASS HLS Compiler☆29Updated last year
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆166Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆36Updated 4 years ago
- IREE plugin repository for the AMD AIE accelerator☆100Updated this week
- CGRA Compilation Framework☆84Updated 2 years ago