Xilinx Modifications to Halide
☆13May 3, 2021Updated 5 years ago
Alternatives and similar repositories for vyasa
Users that are interested in vyasa are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE☆17Aug 5, 2022Updated 3 years ago
- ☆25Updated this week
- IREE plugin repository for the AMD AIE accelerator☆132Jun 9, 2026Updated last week
- ☆140Jun 11, 2026Updated last week
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆22Apr 17, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆18Dec 29, 2024Updated last year
- Symbolic range analysis for LLVM.☆12Jan 10, 2016Updated 10 years ago
- Fork of LLVM to support AMD AIEngine processors☆202Updated this week
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Aug 26, 2024Updated last year
- An MLIR-based toolchain for AMD AI Engine-enabled devices.☆656Updated this week
- Generator for MLIR files from known front-ends☆16Oct 31, 2023Updated 2 years ago
- [FPGA 2023] FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs☆25Feb 14, 2023Updated 3 years ago
- A scalable High-Level Synthesis framework on MLIR☆299May 15, 2024Updated 2 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆173Mar 12, 2026Updated 3 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM☆124Nov 4, 2024Updated last year
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Dec 16, 2021Updated 4 years ago
- ☆29Nov 29, 2025Updated 6 months ago
- Open-source AI acceleration on FPGA: from ONNX to RTL☆54Jun 4, 2026Updated 2 weeks ago
- SCARIF is a tool to estimate the embodied carbon emissions of data center servers with accelerator hardware (GPUs, FPGAs, etc.)☆15Updated this week
- ☆12May 25, 2021Updated 5 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆36Mar 12, 2026Updated 3 months ago
- A tracing JIT compiler for PyTorch☆14Dec 11, 2021Updated 4 years ago
- Vitis Model Composer Examples and Tutorials☆128Jun 3, 2026Updated 2 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆17May 19, 2023Updated 3 years ago
- ☆63Mar 24, 2025Updated last year
- ☆16Oct 29, 2021Updated 4 years ago
- C/C++ frontend for MLIR. Also features polyhedral optimizations, parallel optimizations, and more!☆617Jun 19, 2025Updated 11 months ago
- 2016 Example repository for creating website graphs with c3.js from CSV files.☆12Oct 6, 2020Updated 5 years ago
- tutorials about polyhedral compilation.☆65Jun 6, 2026Updated last week
- AMD Ryzen™ AI Software includes the tools and runtime libraries for optimizing and deploying AI inference on AMD Ryzen™ AI powered PCs.☆834Apr 17, 2026Updated 2 months ago
- OpenWrt-6.x for JDC AX1800 Pro | 京东云无线宝亚瑟 AX1800 Pro☆12Jul 29, 2024Updated last year
- ☆13Aug 1, 2024Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆17Jun 5, 2024Updated 2 years ago
- Base code and optimized code for the benchmarks used in the PolyMage paper published at ASPLOS 2015☆20Jun 14, 2016Updated 10 years ago
- Open-source of MSD framework☆16Sep 12, 2023Updated 2 years ago
- Allo Accelerator Design and Programming Framework (PLDI'24)☆386Updated this week
- DASS HLS Compiler☆31Oct 4, 2023Updated 2 years ago
- An accelerator to which you can offload RE matching☆14Dec 22, 2024Updated last year
- The Riallto Open Source Project from AMD☆86Apr 10, 2025Updated last year