Alternatives and similar repositories for vyasa

Users that are interested in vyasa are comparing it to the libraries listed below

• hanchenye / polyaie
  An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE
  ☆16Updated 3 years ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆59Updated last year
• Xilinx / merlin-compiler
  ☆58Updated 2 years ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆63Updated 11 months ago
• esa-tu-darmstadt / spn-compiler
  Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.
  ☆24Updated 10 months ago
• Xilinx / mlir-air
  ☆107Updated last week
• StanfordAHA / aha
  ☆61Updated this week
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆50Updated 2 years ago
• Xilinx / aie-rt
  ☆21Updated last month
• cornell-zhang / hcl-dialect
  HeteroCL-MLIR dialect for accelerator design
  ☆41Updated last year
• cucapra / EventQueue
  EQueue Dialect
  ☆40Updated 3 years ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆74Updated last month
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆41Updated 8 months ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆129Updated 5 years ago
• sfu-arch / SpGEMM
  ☆36Updated 4 years ago
• rehohoho / onnx2versal
  Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.
  ☆14Updated 9 months ago
• Xilinx / xup_aie_training
  Hands-on experience programming AI Engines using Vitis Unified Software Platform
  ☆40Updated last year
• kumasento / polsca
  Polyhedral High-Level Synthesis in MLIR
  ☆33Updated 2 years ago
• lana555 / dynamatic
  ☆87Updated last year
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆59Updated 6 months ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆77Updated 6 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆97Updated last year
• pnnl / soda-opt
  ☆49Updated 3 months ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• CMU-SAFARI / SPARTA
  A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…
  ☆22Updated 2 years ago
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• Xilinx / ACCL
  Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators
  ☆97Updated 3 months ago
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆88Updated 2 years ago
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆131Updated last year
• UCLA-VAST / soda-compiler
  Stencil with Optimized Dataflow Architecture Compiler
  ☆17Updated 5 years ago