stephenneuendorffer / vyasaLinks
Xilinx Modifications to Halide
☆13Updated 4 years ago
Alternatives and similar repositories for vyasa
Users that are interested in vyasa are comparing it to the libraries listed below
Sorting:
- Polyhedral High-Level Synthesis in MLIR☆31Updated 2 years ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆23Updated 6 months ago
- HeteroCL-MLIR dialect for accelerator design☆40Updated 8 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 7 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆49Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆40Updated 2 weeks ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆14Updated 5 months ago
- EQueue Dialect☆40Updated 3 years ago
- ☆24Updated 4 years ago
- A hardware synthesis framework with multi-level paradigm☆39Updated 4 months ago
- A Language for Closed-form High-level ARchitecture Modeling☆20Updated 5 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆29Updated 2 months ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 9 months ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆31Updated last year
- ☆58Updated last year
- ☆15Updated 2 years ago
- ☆59Updated this week
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- ☆29Updated 6 years ago
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆14Updated 2 years ago
- ☆35Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- ☆19Updated this week
- ☆15Updated 4 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆60Updated 3 years ago
- A polyhedral compiler for hardware accelerators☆57Updated 10 months ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆59Updated 3 months ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆21Updated 3 weeks ago