UIUC-ChenLab / Chrysalis-HLSLinks
☆15Updated last year
Alternatives and similar repositories for Chrysalis-HLS
Users that are interested in Chrysalis-HLS are comparing it to the libraries listed below
Sorting:
- An open-source benchmark for generating design RTL with natural language☆150Updated last year
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆75Updated 8 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆72Updated 8 months ago
- ☆51Updated last year
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆53Updated 11 months ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆68Updated 4 months ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆78Updated 7 months ago
- ☆50Updated 2 weeks ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆69Updated 2 months ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆17Updated last year
- ☆13Updated 2 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆59Updated 6 months ago
- ☆33Updated last year
- ☆61Updated 8 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆30Updated 2 years ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆55Updated 4 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆71Updated last month
- ☆32Updated last year
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆21Updated 8 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆35Updated this week
- Dataset for ML-guided Accelerator Design☆42Updated last year
- An integrated CGRA design framework☆91Updated 8 months ago
- MICRO 2024 Evaluation Artifact for FuseMax☆16Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆72Updated last year
- A toolchain for rapid design space exploration of chiplet architectures☆68Updated 4 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- An Open-Source Tool for CGRA Accelerators☆77Updated 3 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆33Updated last year