Alternatives and similar repositories for Chrysalis-HLS

Users that are interested in Chrysalis-HLS are comparing it to the libraries listed below

• GATECH-EIC / mg-verilog
  ☆46Updated 8 months ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆31Updated 7 months ago
• hkust-zhiyao / PANDA
  PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
  ☆16Updated last year
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆50Updated 3 weeks ago
• magicYang1573 / llm-hardware-test-generation
  ☆31Updated 11 months ago
• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆42Updated 6 months ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆112Updated 7 months ago
• yaoxufeng / RTLRewriter-Bench
  ☆31Updated last year
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆18Updated last year
• UIUC-ChenLab / Nimblock
  ☆13Updated 2 years ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆30Updated 10 months ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆47Updated 2 months ago
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆24Updated 2 years ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆37Updated 7 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆79Updated 3 years ago
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆32Updated this week
• arc-research-lab / AIM
  AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…
  ☆23Updated last month
• Yinxiao-Feng / chiplet-network-sim
  ☆33Updated 3 weeks ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆59Updated 8 months ago
• OswaldHe / LevelST
  [FPGA 2024] Source code and bitstream for LevelST: Stream-based Accelerator for Sparse Triangular Solver
  ☆12Updated 3 weeks ago
• pku-dasys / easymac
  ☆16Updated 3 years ago
• UCLA-VAST / Stream-HLS
  An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs
  ☆38Updated last month
• hngenc / stellar
  ☆30Updated 7 months ago
• ecolab-nus / morpher-v2
  An Open-Source Tool for CGRA Accelerators
  ☆21Updated last year
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆18Updated last month
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆25Updated last year
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆67Updated 2 months ago
• mec-UMN / HISIM
  HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…
  ☆38Updated 3 months ago
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆33Updated 2 months ago