An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
☆73Sep 29, 2025Updated 5 months ago
Alternatives and similar repositories for GeneSys
Users that are interested in GeneSys are comparing it to the libraries listed below
Sorting:
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆76Updated this week
- ☆62Mar 24, 2025Updated 11 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆85Aug 28, 2023Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Jul 17, 2023Updated 2 years ago
- ☆29Nov 5, 2021Updated 4 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Jul 22, 2025Updated 7 months ago
- Berkeley's Spatial Array Generator☆1,225Updated this week
- A co-design architecture on sparse attention☆55Aug 23, 2021Updated 4 years ago
- Repository to host and maintain SCALE-Sim code☆417Feb 2, 2026Updated last month
- ☆224Oct 24, 2025Updated 4 months ago
- A general framework for optimizing DNN dataflow on systolic array☆39Jan 2, 2021Updated 5 years ago
- ☆43Mar 31, 2025Updated 11 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆187Jan 8, 2026Updated last month
- Collection of kernel accelerators optimised for LLM execution☆27Updated this week
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆133May 10, 2024Updated last year
- A scalable High-Level Synthesis framework on MLIR☆289May 15, 2024Updated last year
- CMake based hardware build system☆35Updated this week
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆75Jun 30, 2024Updated last year
- ☆28Feb 26, 2023Updated 3 years ago
- The source code of "Agents of Autonomy: A Systematic Study of Robotics on Modern Hardware" paper☆29Dec 18, 2023Updated 2 years ago
- Processing in Memory Emulation☆23Feb 24, 2023Updated 3 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆82Mar 12, 2025Updated 11 months ago
- Explore the energy-efficient dataflow scheduling for neural networks.☆233Aug 24, 2020Updated 5 years ago
- DUTH RISC V Microprocessor for High Level Synthesis☆10Jun 23, 2023Updated 2 years ago
- ☆13Jul 25, 2024Updated last year
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆14Aug 25, 2023Updated 2 years ago
- ConFuzz is an advanced FPGA configuration engine fuzzing and rapid prototyping framework based on boofuzz and OpenOCD.☆15Nov 3, 2025Updated 4 months ago
- Securing Deep Spiking Neural Networks against Adversarial Attacks through Inherent Structural Parameters☆13Aug 15, 2022Updated 3 years ago
- Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.☆459Feb 19, 2026Updated last week
- Simulator for BitFusion☆101Aug 6, 2020Updated 5 years ago
- The wafer-native AI accelerator simulation platform and inference engine.☆50Jan 1, 2026Updated 2 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆164Feb 24, 2026Updated last week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Feb 6, 2020Updated 6 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Aug 2, 2019Updated 6 years ago
- An open-sourced PyTorch library for developing energy efficient multiplication-less models and applications.☆14Feb 3, 2025Updated last year
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆38May 17, 2024Updated last year
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆185Jan 23, 2026Updated last month
- ☆18May 1, 2024Updated last year
- ☆13Aug 1, 2024Updated last year