actlab-genesys / GeneSysLinks
An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
☆53Updated 2 months ago
Alternatives and similar repositories for GeneSys
Users that are interested in GeneSys are comparing it to the libraries listed below
Sorting:
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆53Updated last month
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆53Updated 2 months ago
- ☆53Updated 2 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 10 months ago
- A co-design architecture on sparse attention☆52Updated 3 years ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆118Updated 3 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- RTL implementation of Flex-DPE.☆100Updated 5 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆43Updated last year
- Serpens is an HBM FPGA accelerator for SpMV☆19Updated 10 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆36Updated last year
- [FPGA 2024] Source code and bitstream for LevelST: Stream-based Accelerator for Sparse Triangular Solver☆12Updated this week
- ☆45Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆91Updated 8 months ago
- ☆16Updated 3 weeks ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆67Updated 2 months ago
- ☆9Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated last month
- ☆29Updated 6 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆55Updated 5 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- An Open-Source Tool for CGRA Accelerators☆65Updated last month
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆80Updated last month
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆57Updated 3 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated 11 months ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated 2 years ago
- ☆39Updated 5 months ago