actlab-genesys / GeneSysLinks
An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
☆57Updated 3 months ago
Alternatives and similar repositories for GeneSys
Users that are interested in GeneSys are comparing it to the libraries listed below
Sorting:
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆54Updated this week
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆54Updated 3 months ago
- A co-design architecture on sparse attention☆52Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 10 months ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆46Updated last year
- ☆55Updated 3 months ago
- ☆47Updated 3 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆38Updated last year
- RTL implementation of Flex-DPE.☆103Updated 5 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆56Updated 6 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆18Updated 2 months ago
- ☆30Updated 7 months ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆53Updated 2 months ago
- STONNE: A Simulation Tool for Neural Networks Engines☆132Updated last week
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆92Updated 8 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆126Updated 4 months ago
- ☆17Updated last month
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆68Updated 3 months ago
- Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"☆28Updated 6 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆81Updated last month
- ☆41Updated 11 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆72Updated 6 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆57Updated 3 years ago
- [FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS☆13Updated 4 months ago
- ☆31Updated 4 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆81Updated last year