actlab-genesys / GeneSysLinks
An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
☆68Updated 3 weeks ago
Alternatives and similar repositories for GeneSys
Users that are interested in GeneSys are comparing it to the libraries listed below
Sorting:
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆60Updated 3 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆67Updated last month
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆86Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆81Updated 3 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆33Updated this week
- ☆48Updated 2 months ago
- ☆60Updated 7 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆72Updated 6 months ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆18Updated 6 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆97Updated 5 months ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆53Updated 2 months ago
- RTL implementation of Flex-DPE.☆113Updated 5 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- ☆32Updated 11 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆162Updated 2 months ago
- ☆48Updated 4 years ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆157Updated 8 months ago
- STONNE: A Simulation Tool for Neural Networks Engines☆140Updated 4 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆157Updated this week
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆52Updated last year
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆41Updated 3 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆65Updated 10 months ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆58Updated last week
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆76Updated 7 months ago
- A co-design architecture on sparse attention☆53Updated 4 years ago
- ☆12Updated 2 years ago
- ☆68Updated 2 weeks ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆47Updated last year