Alternatives and similar repositories for mlir-vitis

Users that are interested in mlir-vitis are comparing it to the libraries listed below

• UCLA-VAST / heterohalide
  HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
  ☆15Updated 5 years ago
• hanchenye / polyaie
  An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE
  ☆18Updated 3 years ago
• sfu-arch / muir
  ☆24Updated 5 years ago
• cornell-zhang / hcl-dialect
  HeteroCL-MLIR dialect for accelerator design
  ☆42Updated last year
• RalphMao / EIE-simulator
  C++ RTL simulator for EIE(https://arxiv.org/abs/1602.01528)
  ☆23Updated 4 years ago
• sfu-arch / SpGEMM
  ☆36Updated 4 years ago
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 3 years ago
• suchandler96 / gem5-NVDLA
  ☆42Updated 10 months ago
• kumasento / polsca
  Polyhedral High-Level Synthesis in MLIR
  ☆35Updated 2 years ago
• pku-liang / HASCO
  agile hardware-software co-design
  ☆52Updated 4 years ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆53Updated 2 years ago
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆61Updated 4 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆50Updated 11 months ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆83Updated 7 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• fpgasystems / GPU-FPGA-Recommendation-System
  FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters
  ☆17Updated 4 years ago
• cucapra / EventQueue
  EQueue Dialect
  ☆41Updated 3 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆62Updated 3 months ago
• esa-tu-darmstadt / spn-compiler
  Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.
  ☆25Updated last year
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆74Updated last month
• ic-lab-duth / Fast-Float4HLS
  Fast Floating Point Operators for High Level Synthesis
  ☆23Updated 2 years ago
• microsoft / brainsmith
  Open-source AI acceleration on FPGA: from ONNX to RTL
  ☆46Updated 3 weeks ago
• cornell-zhang / uptune
  A Generic Distributed Auto-Tuning Infrastructure
  ☆24Updated 4 years ago
• cornell-zhang / allo-pldi24-artifact
  Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"
  ☆33Updated last year
• cornell-zhang / GraphLily
  A graph linear algebra overlay
  ☆51Updated 2 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆30Updated 2 years ago
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆43Updated last year
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆40Updated 3 years ago