Alternatives and similar repositories for mlir-vitis

Users that are interested in mlir-vitis are comparing it to the libraries listed below

• cornell-zhang / hcl-dialect
  HeteroCL-MLIR dialect for accelerator design
  ☆42Updated last year
• esa-tu-darmstadt / spn-compiler
  Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.
  ☆24Updated last year
• kumasento / polsca
  Polyhedral High-Level Synthesis in MLIR
  ☆34Updated 2 years ago
• UCLA-VAST / heterohalide
  HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
  ☆15Updated 5 years ago
• hanchenye / polyaie
  An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE
  ☆16Updated 3 years ago
• cucapra / EventQueue
  EQueue Dialect
  ☆41Updated 3 years ago
• union-codesign / union
  ☆14Updated 4 years ago
• sfu-arch / muir
  ☆24Updated 5 years ago
• he-actlab / polymath
  ☆22Updated 9 months ago
• cornell-zhang / eqmap
  Using e-graphs for logic synthesis
  ☆24Updated last month
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 3 years ago
• cornell-zhang / allo-pldi24-artifact
  Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"
  ☆30Updated last year
• pku-liang / HASCO
  agile hardware-software co-design
  ☆52Updated 3 years ago
• sfu-arch / SpGEMM
  ☆37Updated 4 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆82Updated 6 years ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆34Updated 2 years ago
• suchandler96 / gem5-NVDLA
  ☆40Updated 8 months ago
• icgrp / hipr
  ☆16Updated 2 years ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆52Updated 2 years ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆59Updated last year
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆96Updated last year
• Accelergy-Project / processing-in-memory-design
  ☆25Updated last year
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆30Updated 2 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆60Updated 4 years ago
• cornell-zhang / uptune
  A Generic Distributed Auto-Tuning Infrastructure
  ☆22Updated 4 years ago
• RalphMao / EIE-simulator
  C++ RTL simulator for EIE(https://arxiv.org/abs/1602.01528)
  ☆23Updated 4 years ago
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆41Updated 10 months ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆82Updated 6 years ago
• maestro-project / confuciux
  ☆32Updated 4 years ago