heterosys / mlir-vitis
π₯ π― (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.
β13Updated 2 years ago
Alternatives and similar repositories for mlir-vitis:
Users that are interested in mlir-vitis are comparing it to the libraries listed below
- Polyhedral High-Level Synthesis in MLIRβ30Updated last year
- HeteroCL-MLIR dialect for accelerator designβ41Updated 5 months ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Accelerationβ15Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory maβ¦β20Updated last week
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.β23Updated 2 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Designβ25Updated last month
- β23Updated 4 years ago
- β15Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCeleratorsβ28Updated last year
- A hardware synthesis framework with multi-level paradigmβ36Updated last month
- Domain-Specific Architecture Generator 2β21Updated 2 years ago
- β12Updated 6 months ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)β38Updated 2 months ago
- β20Updated this week
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clustersβ16Updated 3 years ago
- A graph linear algebra overlayβ51Updated last year
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA acceleratβ¦β19Updated 5 months ago
- agile hardware-software co-designβ47Updated 3 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.β48Updated last year
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLSβ18Updated 5 years ago
- Fibertree emulatorβ12Updated 3 months ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)β31Updated 9 months ago
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/β¦β18Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLSβ84Updated 4 months ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLSβ11Updated 3 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Pageβ20Updated 3 weeks ago
- Example for running IREE in a bare-metal Arm environment.β29Updated last month
- β34Updated 3 years ago
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"β19Updated 10 months ago
- A polyhedral compiler for hardware acceleratorsβ55Updated 6 months ago