arc-research-lab / SSRLinks
SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
☆32Updated this week
Alternatives and similar repositories for SSR
Users that are interested in SSR are comparing it to the libraries listed below
Sorting:
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆46Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 10 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆54Updated this week
- A co-design architecture on sparse attention☆52Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆57Updated 3 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 3 years ago
- ☆47Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆92Updated 8 months ago
- Open-source of MSD framework☆16Updated last year
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆63Updated 5 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆54Updated 3 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated 11 months ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 2 years ago
- ☆17Updated last month
- ☆17Updated 9 months ago
- ☆59Updated last week
- ☆27Updated 2 months ago
- Implementation of Microscaling data formats in SystemVerilog.☆20Updated 9 months ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆28Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆53Updated 2 months ago
- Collection of kernel accelerators optimised for LLM execution☆18Updated 2 months ago
- ☆35Updated 4 years ago
- ☆44Updated 2 years ago
- RTL implementation of Flex-DPE.☆103Updated 5 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆16Updated 6 years ago
- ☆41Updated 11 months ago
- Serpens is an HBM FPGA accelerator for SpMV☆19Updated 10 months ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆18Updated 2 months ago