arc-research-lab / SSR
SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
☆29Updated 7 months ago
Alternatives and similar repositories for SSR:
Users that are interested in SSR are comparing it to the libraries listed below
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆77Updated 7 months ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆36Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆48Updated 3 weeks ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆69Updated 3 years ago
- Open-source of MSD framework☆16Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆48Updated this week
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆130Updated 2 months ago
- MICRO22 artifact evaluation for Sparseloop☆42Updated 2 years ago
- A co-design architecture on sparse attention☆50Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆46Updated 5 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆86Updated 5 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆37Updated 2 years ago
- ☆52Updated this week
- ☆47Updated 3 weeks ago
- ☆71Updated 2 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆25Updated last year
- ☆25Updated 2 months ago
- RTL implementation of Flex-DPE.☆98Updated 5 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆22Updated last week
- ☆39Updated 8 months ago
- ☆32Updated 4 years ago
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆123Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆45Updated last month