A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https://arxiv.org/pdf/2303.03509.pdf)
☆22Jul 27, 2023Updated 2 years ago
Alternatives and similar repositories for SPARTA
Users that are interested in SPARTA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE☆17Aug 5, 2022Updated 3 years ago
- MoSAIC: Modular system for Acceleration Integration MoSAIC☆10Aug 22, 2025Updated 8 months ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆26May 18, 2025Updated 11 months ago
- This simulator models multi core systems with primary focus on the memory hierarchy. It models a trace-based out-of-order core frontend a…☆12Feb 12, 2016Updated 10 years ago
- An alternative Vivado custom design example (to fully Vitis) for the User Logic Partition targeting VCK5000☆13Jul 16, 2024Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- IREE plugin repository for the AMD AIE accelerator☆128Apr 27, 2026Updated last week
- ☆24Nov 10, 2020Updated 5 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Jul 15, 2021Updated 4 years ago
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆17Dec 29, 2024Updated last year
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Sep 24, 2020Updated 5 years ago
- PIM-ML is a benchmark for training machine learning algorithms on the UPMEM architecture, which is the first publicly-available real-worl…☆25Jan 7, 2025Updated last year
- A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…☆14Aug 23, 2024Updated last year
- ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)☆62Mar 8, 2026Updated last month
- ☆14Dec 15, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. …☆11May 4, 2022Updated 4 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆23Oct 9, 2020Updated 5 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Sep 14, 2020Updated 5 years ago
- EQueue Dialect☆42Feb 3, 2022Updated 4 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆169Mar 12, 2026Updated last month
- ☆13Aug 1, 2024Updated last year
- ☆136Apr 28, 2026Updated last week
- NATSA is the first near-data-processing accelerator for time series analysis based on the Matrix Profile (SCRIMP) algorithm. NATSA exploi…☆16Jun 14, 2023Updated 2 years ago
- ☆17Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Bridging polyhedral analysis tools to the MLIR framework☆119Sep 9, 2023Updated 2 years ago
- ☆63Mar 24, 2025Updated last year
- HWASim is a simulator for heterogeneous systems with CPUs and Hardware Accelerators (HWAs). It is released with the DASH memory scheduler…☆19Jan 11, 2016Updated 10 years ago
- CoMeT is a new low-cost RowHammer mitigation that uses Count-Min Sketch-based aggressor row tracking, as described in our HPCA'24 paper h…☆11Jan 23, 2026Updated 3 months ago
- Fork of LLVM to support AMD AIEngine processors☆196Updated this week
- An MLIR-based toolchain for AMD AI Engine-enabled devices.☆630Updated this week
- A research shell for Alveo V80☆34Apr 28, 2026Updated last week
- su su su supernova☆25Jan 9, 2025Updated last year