[FPGA 2024] Source code and bitstream for LevelST: Stream-based Accelerator for Sparse Triangular Solver
☆15Jun 1, 2025Updated last year
Alternatives and similar repositories for LevelST
Users that are interested in LevelST are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- [FCCM 2025] Code Samples for InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs☆15Mar 26, 2025Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆178Mar 12, 2026Updated 6 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆38Mar 12, 2026Updated 6 months ago
- Serpens is an HBM FPGA accelerator for SpMV☆23Jul 26, 2024Updated 2 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Sep 28, 2026Updated last week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ACM TODAES Best Paper Award, 2022☆35Oct 24, 2023Updated 2 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆50Nov 12, 2024Updated last year
- Try the active community-maintained version with binary releases at https://github.com/tuna/tapa . This is the UCLA publication version.☆194Aug 11, 2026Updated last month
- Filament sensor inside Mini AB☆14Oct 21, 2021Updated 4 years ago
- RTL code for the DPU chip designed for irregular graphs☆14May 30, 2022Updated 4 years ago
- [NAACL 2025] Official Implementation of "HMT: Hierarchical Memory Transformer for Long Context Language Processing"☆80Mar 12, 2026Updated 6 months ago
- A sample code for sparse cholesky solver with cuSPARSE and cuSOLVER library☆21Dec 19, 2019Updated 6 years ago
- A tool designed to compare energy and emission costs between computer chips☆13Dec 9, 2023Updated 2 years ago
- Starting from Attention, teaching the realization of VIT and other vision Transformer models hand in hand.☆12Nov 20, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A DAG processor and compiler for a tree-based spatial datapath.☆17Aug 24, 2022Updated 4 years ago
- ☆12Mar 3, 2025Updated last year
- Top-down shooter game written in C++ w/ Qt for my CSCI102 final project.☆15Apr 30, 2012Updated 14 years ago
- 马督工视频文稿 + 分析 + 学习☆15Jul 16, 2026Updated 2 months ago
- Large-scale medical image processing and reconstruction toolbox☆18Feb 13, 2024Updated 2 years ago
- I love Database.☆17Dec 25, 2024Updated last year
- Toolkit for launching and observing MaxText training on Slurm-managed GPU clusters☆29Jul 19, 2026Updated 2 months ago
- ☆16May 23, 2024Updated 2 years ago
- ☆35Mar 1, 2019Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆35Apr 20, 2021Updated 5 years ago
- ☆14May 19, 2023Updated 3 years ago
- ☆22Sep 22, 2024Updated 2 years ago
- Harnessing FABRIC for Scalable Human Genome Sequence Analysis☆13May 9, 2026Updated 5 months ago
- ☆18Aug 17, 2026Updated last month
- ☆14Feb 14, 2022Updated 4 years ago
- An HBM FPGA based SpMV Accelerator☆19Aug 29, 2024Updated 2 years ago
- Support material for the Building Accelerated Applications with Vitis webinar series☆17Sep 10, 2020Updated 6 years ago
- Evolvable Hardware: Begin using the BitstreamEvolution Open Source Toolkit☆18May 28, 2026Updated 4 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- a general-purpose machine learning-driven auto-tuner for heterogeneous platforms☆10Sep 7, 2024Updated 2 years ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆32Mar 5, 2021Updated 5 years ago
- ☆16Aug 21, 2019Updated 7 years ago
- ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)☆68Mar 8, 2026Updated 7 months ago
- DaCH: dataflow cache for high-level synthesis.☆20Jul 27, 2023Updated 3 years ago
- ☆73Feb 16, 2023Updated 3 years ago
- NeuroSim (NS)-Cache is a framework developed for early exploration of cache memories in advanced technology nodes☆19Sep 29, 2026Updated last week