kaiiiz / hls-spmv
High-level synthesis (HLS) implementation of Sparse Matrix Vector Multiplication
☆15Updated 3 years ago
Alternatives and similar repositories for hls-spmv:
Users that are interested in hls-spmv are comparing it to the libraries listed below
- tpu-systolic-array-weight-stationary☆24Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 7 months ago
- eyeriss-chisel3☆40Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆74Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆71Updated last year
- RTL generator for SpGEMM☆12Updated 4 years ago
- C++ code for HLS FPGA implementation of transformer☆16Updated 7 months ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆65Updated 2 months ago
- ☆15Updated 10 months ago
- ☆32Updated 7 months ago
- Open-source of MSD framework☆16Updated last year
- ☆35Updated last month
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆98Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆37Updated 9 months ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- ☆63Updated 6 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated 2 months ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 4 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆27Updated last year
- An Open-Source Tool for CGRA Accelerators☆64Updated last week
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 3 years ago
- a Computing In Memory emULATOR framework☆11Updated 11 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆155Updated 5 years ago
- Ratatoskr NoC Simulator☆24Updated 4 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆50Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆39Updated 6 months ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆30Updated 2 years ago