Alternatives and similar repositories for SPAGHETTI

Users that are interested in SPAGHETTI are comparing it to the libraries listed below

• lsq314 / SpMM_TCAD
  ☆17Updated 11 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• SET-Scheduling-Project / GEMINI-HPCA2024
  Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
  ☆87Updated 4 months ago
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆28Updated 2 years ago
• SET-Scheduling-Project / SET-ISCA2023
  The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.
  ☆69Updated 5 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆58Updated last month
• kelvin0207 / SparSynergy
  Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…
  ☆17Updated 4 months ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆110Updated 5 years ago
• Yinxiao-Feng / chiplet-network-sim
  ☆40Updated 2 months ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆58Updated last week
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆62Updated 8 months ago
• scalesim-project / scale-sim-v3
  ☆41Updated 2 weeks ago
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆51Updated 4 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated 11 months ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆44Updated 3 years ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆62Updated 5 months ago
• UCLA-VAST / Serpens
  Serpens is an HBM FPGA accelerator for SpMV
  ☆19Updated last year
• gem5-X / TiC-SAT
  ☆17Updated 3 months ago
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆35Updated 2 months ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆150Updated this week
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆32Updated 3 months ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• GraphSAINT / GNN-ARCH
  [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
  ☆41Updated 4 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆83Updated last year
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆67Updated 4 months ago
• gkrish19 / SIAM-Chiplet-based-Scalable-In-Memory-Acceleration-with-Mesh-for-Deep-Neural-Networks
  A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.
  ☆23Updated last year
• Chun-Feng / CACTI-6.0
  ASIC simulation of Multi-ported Memory Module. And it can offer SRAM-based dual-port basic building block to support multiple read/write …
  ☆21Updated 9 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆64Updated 3 years ago
• baichen318 / boom-explorer-public
  The open-sourced version of BOOM-Explorer
  ☆43Updated 2 years ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆29Updated 3 years ago