jeffreyyu0602 / quantized-training
☆21Updated this week
Alternatives and similar repositories for quantized-training:
Users that are interested in quantized-training are comparing it to the libraries listed below
- Tender: Accelerating Large Language Models via Tensor Decompostion and Runtime Requantization (ISCA'24)☆13Updated 6 months ago
- A co-design architecture on sparse attention☆48Updated 3 years ago
- ☆42Updated 3 years ago
- ☆85Updated last year
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆81Updated 4 months ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆24Updated 10 months ago
- MICRO22 artifact evaluation for Sparseloop☆41Updated 2 years ago
- mixed-precision quantization for LLMs☆18Updated last year
- ViTALiTy (HPCA'23) Code Repository☆20Updated last year
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆33Updated last year
- Implementation of Microscaling data formats in SystemVerilog.☆13Updated 4 months ago
- ☆16Updated last month
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆46Updated this week
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆35Updated last year
- ☆25Updated last month
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆25Updated 7 months ago
- ☆31Updated 4 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆47Updated this week
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆65Updated 4 months ago
- Open-source of MSD framework☆16Updated last year
- PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training☆15Updated 7 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆43Updated 3 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆44Updated last month
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆58Updated this week
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆118Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆38Updated last week
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆83Updated last month
- RTL implementation of Flex-DPE.☆97Updated 4 years ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆102Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆67Updated 3 years ago