jeffreyyu0602 / quantized-trainingLinks
☆34Updated last month
Alternatives and similar repositories for quantized-training
Users that are interested in quantized-training are comparing it to the libraries listed below
Sorting:
- ☆113Updated 2 years ago
- A co-design architecture on sparse attention☆55Updated 4 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆31Updated last year
- ☆48Updated 4 years ago
- Tender: Accelerating Large Language Models via Tensor Decompostion and Runtime Requantization (ISCA'24)☆24Updated last year
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆119Updated last year
- ☆29Updated 3 months ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆85Updated 9 months ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆55Updated 2 years ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆126Updated 2 years ago
- Official implementation of EMNLP'23 paper "Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference?"☆24Updated 2 years ago
- [TRETS 2025][FPGA 2024] FPGA Accelerator for Imbalanced SpMV using HLS☆19Updated 5 months ago
- Implementation of Microscaling data formats in SystemVerilog.☆29Updated 6 months ago
- MICRO22 artifact evaluation for Sparseloop☆46Updated 3 years ago
- ViTALiTy (HPCA'23) Code Repository☆23Updated 2 years ago
- ☆26Updated 11 months ago
- [HPCA 2026] Official implementation of "Focus: A Streaming Concentration Architecture for Efficient Vision-Language Models"☆25Updated last month
- ☆35Updated 5 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆107Updated 8 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆46Updated last year
- Simulator for BitFusion☆102Updated 5 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆71Updated 3 months ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 6 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆35Updated this week
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆43Updated 2 years ago
- ☆15Updated last year
- A bit-level sparsity-awared multiply-accumulate process element.☆18Updated last year
- ☆218Updated 3 months ago