jeffreyyu0602 / quantized-trainingLinks
☆31Updated last week
Alternatives and similar repositories for quantized-training
Users that are interested in quantized-training are comparing it to the libraries listed below
Sorting:
- ☆51Updated 2 months ago
- ☆112Updated last year
- A co-design architecture on sparse attention☆52Updated 4 years ago
- Tender: Accelerating Large Language Models via Tensor Decompostion and Runtime Requantization (ISCA'24)☆20Updated last year
- ☆48Updated 4 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆29Updated last year
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆51Updated last year
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆106Updated last year
- Official implementation of EMNLP'23 paper "Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference?"☆23Updated last year
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆117Updated 2 years ago
- Implementation of Microscaling data formats in SystemVerilog.☆24Updated 3 months ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆66Updated 5 months ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆47Updated last year
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆95Updated 5 months ago
- [TRETS 2025][FPGA 2024] FPGA Accelerator for Imbalanced SpMV using HLS☆14Updated last month
- Open-source of MSD framework☆16Updated 2 years ago
- ☆35Updated 5 years ago
- ☆47Updated last month
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆66Updated last week
- Model LLM inference on single-core dataflow accelerators☆14Updated last month
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆18Updated 6 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆59Updated 3 months ago
- RTL implementation of Flex-DPE.☆112Updated 5 years ago
- ViTALiTy (HPCA'23) Code Repository☆23Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆64Updated 2 weeks ago
- PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training☆18Updated last year
- Simulator for BitFusion☆102Updated 5 years ago
- ☆66Updated last week