asyncvlsi / lefdefLinks
Mirror of the Si2 LEF/DEF parser (v5.8)
☆18Updated 4 years ago
Alternatives and similar repositories for lefdef
Users that are interested in lefdef are comparing it to the libraries listed below
Sorting:
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆156Updated 3 weeks ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆142Updated 2 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆137Updated last year
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆142Updated 2 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆190Updated 8 months ago
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆88Updated last year
- ☆50Updated 2 years ago
- Artificial Netlist Generator☆46Updated last year
- DATC RDF☆50Updated 5 years ago
- RePlAce global placement tool☆246Updated 5 years ago
- ☆61Updated 4 years ago
- UCSD Detailed Router☆96Updated 5 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆60Updated 5 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆109Updated last year
- ☆36Updated 5 years ago
- GT3 PDK☆21Updated 2 months ago
- Timing prediction dataset download and instructions.☆17Updated 2 years ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆31Updated 3 years ago
- Collection of digital hardware modules & projects (benchmarks)☆80Updated 2 months ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆61Updated last year
- GPU-based logic synthesis tool☆97Updated 2 months ago
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆54Updated last year
- ☆95Updated 7 months ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆62Updated 7 months ago
- Analog Placement Quality Prediction☆25Updated 2 years ago
- ☆27Updated last year
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆76Updated 3 weeks ago
- Machine Generated Analog IC Layout☆267Updated last year
- ☆40Updated 4 years ago
- ☆30Updated 9 months ago