Alternatives and similar repositories for lefdef

Users that are interested in lefdef are comparing it to the libraries listed below

• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆133Updated last month
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆127Updated last year
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆76Updated 11 months ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆29Updated 3 years ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆137Updated 2 years ago
• cuhk-eda / cu-gr-2
  ☆44Updated last year
• ABKGroup / TritonRoute-WXL
  ☆31Updated 4 years ago
• The-OpenROAD-Project / RePlAce
  RePlAce global placement tool
  ☆236Updated 4 years ago
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆135Updated 2 years ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆105Updated last year
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆75Updated 7 years ago
• ABKGroup / PlacementEssentialReadings
  ☆57Updated 4 years ago
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆44Updated 9 months ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆39Updated last year
• TimingPredict / Dataset
  Timing prediction dataset download and instructions.
  ☆15Updated 2 years ago
• Daikon-Sun / Physical-Design-for-Nanometer-ICs
  Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)
  ☆41Updated 6 years ago
• bu-icsg / TAP-2.5D
  ☆34Updated 4 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆86Updated last month
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆90Updated 4 years ago
• EricLu1218 / Physical_Design_Automation
  2019 NTHU CS6135 (CS613500) VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing …
  ☆39Updated 2 months ago
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆47Updated last month
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆175Updated 2 months ago
• TILOS-AI-Institute / HypergraphPartitioning
  Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes
  ☆70Updated 2 months ago
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆41Updated last month
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆54Updated 6 months ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆58Updated 4 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated 2 weeks ago
• PKU-IDEA / OpenPARF
  🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
  ☆151Updated 3 months ago
• CODA-Team / AncstrGNN_benchmark
  Analog IC symmetry extraction benchmark of AncstrGNN
  ☆10Updated 11 months ago