mgwoo / RePlAce

Related projects ⓘ

Alternatives and complementary repositories for RePlAce

• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆32Updated 7 months ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆26Updated 2 years ago
• ABKGroup / TritonRoute-WXL
  ☆25Updated 4 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆67Updated 3 months ago
• cuhk-eda / Xplace
  Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
  ☆97Updated 4 months ago
• ABKGroup / PROBE_SMT_AutoCell
  ☆17Updated last year
• cuhk-eda / cu-gr-2
  ☆35Updated 10 months ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆122Updated 3 months ago
• zshi0616 / DeepGate2
  ☆27Updated 11 months ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆48Updated 4 years ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆121Updated last year
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 4 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆31Updated last week
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆68Updated 6 years ago
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆128Updated last year
• ABKGroup / PlacementEssentialReadings
  ☆49Updated 3 years ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆33Updated last month
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆63Updated 2 months ago
• asyncvlsi / SPRoute
  A parallel global router using the Galois framework
  ☆25Updated last year
• abk-openroad / BST-DME
  Bounded-Skew DME v1.3
  ☆14Updated 6 years ago
• zshi0616 / python-deepgate
  ☆21Updated 4 months ago
• hkust-zhiyao / APPLE
  A circuit-element level explainer to explain machine learning model's prediction on chip layouts.
  ☆17Updated last year
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆17Updated last month
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆52Updated 4 years ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆97Updated 8 months ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆146Updated last year
• UTDA-group / BoxRouter
  BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…
  ☆20Updated 5 years ago
• alanminko / iwls2022-ls-contest
  Problems and Results of IWLS 2022 Programming Contest
  ☆16Updated 2 years ago
• tsung-wei-huang / ece5960-physical-design
  ☆36Updated last year
• TILOS-AI-Institute / HypergraphPartitioning
  Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes
  ☆58Updated 2 weeks ago