The-OpenROAD-Project / TritonSizerLinks
UCSD Sizer for leakage/dynamic power recovery, timing recovery
☆18Updated 6 years ago
Alternatives and similar repositories for TritonSizer
Users that are interested in TritonSizer are comparing it to the libraries listed below
Sorting:
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Macro placement tool for OpenROAD flow☆24Updated 5 years ago
- Builds, flow and designs for the alpha release☆54Updated 6 years ago
- ☆32Updated 3 years ago
- Intel's Analog Detailed Router☆39Updated 6 years ago
- Open Source Detailed Placement engine☆12Updated 5 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆23Updated 5 years ago
- ☆15Updated 6 years ago
- Qrouter detail router for digital ASIC designs☆57Updated last month
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆19Updated 6 years ago
- ☆23Updated 5 years ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 5 years ago
- BAG framework☆41Updated last year
- Public repository for Task 6 of OpenROAD project. ML-based PDN synthesis and optimization.☆34Updated 2 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆59Updated 5 years ago
- DATC Robust Design Flow.☆36Updated 5 years ago
- ☆19Updated last year
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Updated 2 years ago
- ASTRAN - Automatic Synthesis of Transistor Networks☆65Updated 3 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated last year
- ☆33Updated 5 years ago
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆43Updated 2 weeks ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆31Updated this week
- Circuit release of the MAGICAL project☆40Updated 5 years ago
- ☆44Updated 5 years ago
- OpenDesign Flow Database☆17Updated 7 years ago
- This repo contains the code that runs RL+GNN to optimize LDOs in SKY130 process.☆46Updated last year
- Benchmarks for Yosys development☆24Updated 5 years ago
- An automatic clock gating utility☆51Updated 8 months ago
- Coriolis VLSI EDA Tool (LIP6)☆75Updated last week