recurme / Mixed-Cell-Height_legalizerLinks
☆11Updated last year
Alternatives and similar repositories for Mixed-Cell-Height_legalizer
Users that are interested in Mixed-Cell-Height_legalizer are comparing it to the libraries listed below
Sorting:
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆28Updated 3 years ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆133Updated last month
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆135Updated 2 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆127Updated last year
- CUGR, VLSI Global Routing Tool Developed by CUHK☆137Updated 2 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆175Updated 2 months ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- ☆44Updated last year
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆44Updated 9 months ago
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆70Updated 2 months ago
- VLSI EDA Global Router☆75Updated 7 years ago
- RePlAce global placement tool☆236Updated 4 years ago
- Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)☆41Updated 6 years ago
- UCSD Detailed Router☆90Updated 4 years ago
- ☆17Updated 10 months ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆47Updated last month
- GPU-based logic synthesis tool☆86Updated last month
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆151Updated 3 months ago
- ☆31Updated 4 years ago
- The first version of TritonPart☆28Updated last year
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆58Updated 4 years ago
- ☆12Updated last year
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆31Updated 3 weeks ago
- 2019 NTHU CS6135 (CS613500) VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing …☆39Updated 2 months ago
- ☆34Updated 4 years ago
- Global Router Built for ICCAD Contest 2019☆32Updated 5 years ago
- Open Source Detailed Placement engine☆38Updated 5 years ago
- BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…☆21Updated 6 years ago
- A parallel global router using the Galois framework☆29Updated 2 years ago
- Mirror of the Si2 LEF/DEF parser (v5.8)☆16Updated 3 years ago