recurme / Mixed-Cell-Height_legalizerLinks
☆11Updated last year
Alternatives and similar repositories for Mixed-Cell-Height_legalizer
Users that are interested in Mixed-Cell-Height_legalizer are comparing it to the libraries listed below
Sorting:
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆29Updated 3 years ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆138Updated 3 months ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆137Updated 2 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆177Updated 4 months ago
- ☆46Updated last year
- Rsyn – An Extensible Physical Synthesis Framework☆129Updated last year
- Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)☆43Updated 6 years ago
- VLSI EDA Global Router☆75Updated 7 years ago
- ☆33Updated 4 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆137Updated 2 years ago
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆71Updated 3 months ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆155Updated 4 months ago
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆50Updated 10 months ago
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆77Updated last year
- RePlAce global placement tool☆239Updated 5 years ago
- ☆12Updated last year
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆51Updated 3 months ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆58Updated 5 years ago
- ☆17Updated last year
- UCSD Detailed Router☆90Updated 4 years ago
- The first version of TritonPart☆28Updated last year
- GPU-based logic synthesis tool☆90Updated last month
- NTHU CS6135 VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing Floorplan Design…☆40Updated last week
- BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…☆21Updated 6 years ago
- ☆57Updated 4 years ago
- Collection of digital hardware modules & projects (benchmarks)☆61Updated last week
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆56Updated 8 months ago
- ☆24Updated 3 months ago
- ☆34Updated 4 years ago