Alternatives and similar repositories for lefdef_util

Users that are interested in lefdef_util are comparing it to the libraries listed below

• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆62Updated last year
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆36Updated 5 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆18Updated 5 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆39Updated 5 years ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆91Updated 4 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆58Updated 5 years ago
• Ravenslofty / librecell
  ☆26Updated 4 years ago
• The-OpenROAD-Project-Attic / OpenROAD-Utilities
  Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project
  ☆19Updated 6 years ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆39Updated 6 years ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆62Updated 3 weeks ago
• IntelLabs / FloorSet
  ☆77Updated 3 months ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆75Updated 7 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator
  SMT-based-STDCELL-Layout-Generator
  ☆18Updated 4 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• ABKGroup / RosettaStone
  ☆31Updated 3 years ago
• pkuzjx / eda-collection
  ☆105Updated 5 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• The-OpenROAD-Project / asap5
  ☆34Updated 2 years ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆139Updated 2 years ago
• aolofsson / IDEA
  ☆33Updated 5 years ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆179Updated 4 months ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆109Updated last month
• NVlabs / INSTA
  ☆87Updated 3 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆57Updated 8 months ago
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆47Updated 2 years ago
• ABKGroup / PROBE3.0
  ☆47Updated last year
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆97Updated 3 years ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆32Updated 3 years ago