☆102Mar 3, 2026Updated this week
Alternatives and similar repositories for OpenSTA
Users that are interested in OpenSTA are comparing it to the libraries listed below
Sorting:
- OpenSTA engine☆551Updated this week
- Structural Netlist API (and more) for EDA post synthesis flow development☆135Updated this week
- This package provides a gnucap based qucsator implementation.☆15Feb 3, 2026Updated last month
- Library of open source PDKs☆64Feb 3, 2026Updated last month
- Circuit Automatic Characterization Engine☆53Feb 7, 2025Updated last year
- SystemVerilog synthesis tool☆228Mar 10, 2025Updated 11 months ago
- Source code for LEF/DEF☆11Oct 16, 2018Updated 7 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆449Feb 23, 2026Updated last week
- Delay Calculation ToolKit☆32Aug 7, 2022Updated 3 years ago
- liberty parser (For parsing IC timing lib file)☆67Jul 24, 2023Updated 2 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆129Apr 23, 2023Updated 2 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆23Aug 11, 2020Updated 5 years ago
- RePlAce global placement tool☆246Aug 13, 2020Updated 5 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Nov 10, 2025Updated 3 months ago
- Tiny Tapeout project build tools + chip integration scripts☆30Feb 24, 2026Updated last week
- A RRAM addon for the NCSU FreePDK 45nm☆25Jan 10, 2022Updated 4 years ago
- An automatic clock gating utility☆52Apr 15, 2025Updated 10 months ago
- SiliconCompiler Design Gallery☆59Updated this week
- A C++ VLSI circuit schematic and layout database library☆15Jul 1, 2024Updated last year
- An abstraction library for interfacing EDA tools☆756Feb 18, 2026Updated 2 weeks ago
- Rsyn – An Extensible Physical Synthesis Framework☆137Jul 20, 2024Updated last year
- A High-performance Timing Analysis Tool for VLSI Systems☆690Dec 26, 2025Updated 2 months ago
- Database and Tool Framework for EDA☆123Jan 25, 2021Updated 5 years ago
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆575Updated this week
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Jan 13, 2023Updated 3 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆40Jun 10, 2021Updated 4 years ago
- SystemVerilog frontend for Yosys☆202Feb 22, 2026Updated last week
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆682Feb 25, 2026Updated last week
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆2,466Updated this week
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆60Aug 10, 2020Updated 5 years ago
- ☆83Jan 5, 2026Updated 2 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆334Dec 2, 2025Updated 3 months ago
- An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM☆15Mar 25, 2025Updated 11 months ago
- ☆21Sep 15, 2024Updated last year
- SystemVerilog compiler and language services☆968Updated this week
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆395Feb 25, 2026Updated last week
- Constrained RAndom Verification Enviroment (CRAVE)☆18Nov 23, 2023Updated 2 years ago
- Bounded-Skew DME v1.3☆15Aug 3, 2018Updated 7 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆252Feb 22, 2026Updated last week