parallaxsw / OpenSTALinks
☆70Updated this week
Alternatives and similar repositories for OpenSTA
Users that are interested in OpenSTA are comparing it to the libraries listed below
Sorting:
- Introductory course into static timing analysis (STA).☆94Updated last month
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- ☆24Updated 4 years ago
- IDEA project source files☆106Updated 6 months ago
- ☆44Updated last year
- ☆166Updated 2 months ago
- A Standalone Structural Verilog Parser☆92Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆69Updated 4 years ago
- Qrouter detail router for digital ASIC designs☆57Updated last month
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆61Updated last year
- reference block design for the ASAP7nm library in Cadence Innovus☆44Updated 11 months ago
- Intel's Analog Detailed Router☆38Updated 5 years ago
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆90Updated 5 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆55Updated 4 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆48Updated 4 months ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆177Updated 5 years ago
- Collection of digital hardware modules & projects (benchmarks)☆59Updated 3 weeks ago
- Delay Calculation ToolKit☆31Updated 2 years ago
- UCSD Detailed Router☆87Updated 4 years ago
- ☆41Updated 3 years ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- liberty parser (For parsing IC timing lib file)☆58Updated last year
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆104Updated last year
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆82Updated last month
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆27Updated 5 years ago
- A LEF/DEF Utility.☆30Updated 5 years ago
- ☆146Updated 3 years ago
- ☆42Updated 8 months ago
- Logic synthesis and ABC based optimization☆49Updated 3 weeks ago
- EDA physical synthesis optimization kit☆57Updated last year