The-OpenROAD-Project / yosysLinks
Logic synthesis and ABC based optimization
☆49Updated 2 weeks ago
Alternatives and similar repositories for yosys
Users that are interested in yosys are comparing it to the libraries listed below
Sorting:
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆178Updated 5 years ago
- A Standalone Structural Verilog Parser☆92Updated 3 years ago
- ☆169Updated 3 months ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62Updated last year
- Introductory course into static timing analysis (STA).☆95Updated 2 months ago
- IDEA project source files☆106Updated 7 months ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆102Updated 4 years ago
- AIB Generator: Analog hardware compiler for AIB PHY☆34Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆70Updated 4 years ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- A complete open-source design-for-testing (DFT) Solution☆159Updated 3 weeks ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated 4 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆147Updated last year
- ☆44Updated 5 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- ☆27Updated last week
- ☆105Updated 5 years ago
- SystemVerilog RTL Linter for YoSys☆20Updated 7 months ago
- Open source process design kit for 28nm open process☆59Updated last year
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆84Updated 10 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆45Updated 3 years ago
- ☆40Updated 4 months ago
- ☆149Updated 3 years ago
- ☆71Updated this week
- ☆33Updated 5 years ago
- Home of the Advanced Interface Bus (AIB) specification.☆52Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago