Logic synthesis and ABC based optimization
☆54Mar 4, 2026Updated 2 weeks ago
Alternatives and similar repositories for yosys
Users that are interested in yosys are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- OpenROAD users should look at this repository first for instructions on getting started☆101Apr 3, 2021Updated 4 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆23Aug 11, 2020Updated 5 years ago
- ☆25Dec 16, 2020Updated 5 years ago
- Open Source Detailed Placement engine☆12Feb 19, 2020Updated 6 years ago
- ☆16Jul 16, 2020Updated 5 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Feb 18, 2020Updated 6 years ago
- The source code that empowers OpenROAD Cloud☆12Jun 29, 2020Updated 5 years ago
- ☆15Jan 11, 2024Updated 2 years ago
- OpenSTA engine☆555Updated this week
- UCSD Detailed Router☆95Jan 5, 2021Updated 5 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆59Aug 7, 2022Updated 3 years ago
- Annealing-based PCB placement tool☆43May 26, 2020Updated 5 years ago
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆2,507Updated this week
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆596Updated this week
- Macro placement tool for OpenROAD flow☆25Aug 13, 2020Updated 5 years ago
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆20Aug 20, 2019Updated 6 years ago
- Database and Tool Framework for EDA☆123Jan 25, 2021Updated 5 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆59Aug 10, 2020Updated 5 years ago
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,726Sep 15, 2025Updated 6 months ago
- 5级流水线MIPS-lite微系统（北京工业大学计 组课设）☆10Oct 1, 2021Updated 4 years ago
- Public repository for Task 6 of OpenROAD project. ML-based PDN synthesis and optimization.☆36Jul 6, 2023Updated 2 years ago
- A Standalone Structural Verilog Parser☆99Mar 31, 2022Updated 3 years ago
- Extended and external tests for Verilator testing☆17Mar 11, 2026Updated last week
- ☆35Jul 23, 2020Updated 5 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Builds, flow and designs for the alpha release☆54Dec 18, 2019Updated 6 years ago
- Routing Visualization for Physical Design☆20Dec 24, 2018Updated 7 years ago
- Unofficial nextpnr WebAssembly packages☆17Mar 11, 2026Updated last week
- Virtual Platform for AWS FPGA support☆16Oct 19, 2018Updated 7 years ago
- "High density" digital standard cells for SKY130 provided by SkyWater.☆23Feb 22, 2023Updated 3 years ago
- scripts for automating grading with GitHub Classroom and Moodle☆11May 18, 2020Updated 5 years ago
- The UVM written in Python☆17Dec 26, 2025Updated 2 months ago
- Yosys Open SYnthesis Suite☆4,348Updated this week
- Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !☆14Jun 6, 2019Updated 6 years ago
- The programming runtime and interfaces for ARENA.☆14Sep 14, 2021Updated 4 years ago
- KLayout technology files for FreePDK45☆24Jun 12, 2021Updated 4 years ago
- Random ideas and interesting ideas for things we hope to eventually do.☆86Apr 4, 2022Updated 3 years ago
- ☆26Jul 2, 2024Updated last year
- Qflow full end-to-end digital synthesis flow for ASIC designs☆228Oct 26, 2024Updated last year