AUCOHL / Fault
A complete open-source design-for-testing (DFT) Solution
☆143Updated 2 months ago
Alternatives and similar repositories for Fault:
Users that are interested in Fault are comparing it to the libraries listed below
- Standard Cell Library based Memory Compiler using FF/Latch cells☆138Updated 7 months ago
- Introductory course into static timing analysis (STA).☆79Updated 2 months ago
- A Standalone Structural Verilog Parser☆86Updated 2 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆157Updated 2 months ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆126Updated last year
- ☆121Updated 6 months ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆157Updated 4 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 8 months ago
- Fabric generator and CAD tools☆156Updated this week
- ideas and eda software for vlsi design☆48Updated 3 weeks ago
- Python packages providing a library for Verification Stimulus and Coverage☆116Updated 4 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆264Updated this week
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆244Updated last week
- UVM 1.2 port to Python☆247Updated 10 months ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆42Updated 4 years ago
- OpenROAD users should look at this repository first for instructions on getting started☆102Updated 3 years ago
- SystemVerilog synthesis tool☆177Updated this week
- Advanced Interface Bus (AIB) die-to-die hardware open source☆132Updated 4 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆206Updated 2 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆51Updated 2 years ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆56Updated 8 months ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆72Updated 3 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago
- Altera Advanced Synthesis Cookbook 11.0☆98Updated last year
- ☆78Updated 2 years ago
- Generic Register Interface (contains various adapters)☆103Updated 4 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆130Updated last month
- Test suite designed to check compliance with the SystemVerilog standard.☆306Updated this week
- Control and status register code generator toolchain☆111Updated last month
- An Open-Source Design and Verification Environment for RISC-V☆77Updated 3 years ago