Alternatives and similar repositories for Fault:

Users that are interested in Fault are comparing it to the libraries listed below

• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆144Updated 10 months ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆129Updated last year
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆176Updated last week
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆170Updated 5 years ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆275Updated last week
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆166Updated 5 months ago
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 4 years ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆247Updated 2 months ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆90Updated 5 months ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆172Updated 2 years ago
• The-OpenROAD-Project / asap7
  ☆153Updated last month
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆91Updated 3 years ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆313Updated this week
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆91Updated last week
• chipsalliance / uvm-verilator
  ☆92Updated last year
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆66Updated 3 years ago
• kunalg123 / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆157Updated last year
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated this week
• ncsu-eda / FreePDK3
  ☆138Updated 3 years ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆134Updated 7 months ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆120Updated this week
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆74Updated this week
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆98Updated 4 years ago
• RTimothyEdwards / open_pdks
  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…
  ☆317Updated 2 weeks ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆133Updated last month
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆195Updated last week
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆96Updated last year
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆113Updated 6 months ago
• efabless / chipignite-resources
  ☆79Updated 2 years ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆217Updated 3 weeks ago