A complete open-source design-for-testing (DFT) Solution
☆196Aug 30, 2025Updated 10 months ago
Alternatives and similar repositories for Fault
Users that are interested in Fault are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.☆93May 7, 2024Updated 2 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆172Nov 10, 2025Updated 7 months ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆37Apr 9, 2026Updated 3 months ago
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,849Mar 25, 2026Updated 3 months ago
- An automatic clock gating utility☆53Apr 15, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- OpenSTA engine☆589Jun 29, 2026Updated last week
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆118Jul 2, 2025Updated last year
- 7 track standard cells for GF180MCU provided by GlobalFoundries.☆29Dec 1, 2022Updated 3 years ago
- Logic circuit analysis and optimization☆51Feb 2, 2026Updated 5 months ago
- A library and command-line tool for querying a Verilog netlist.☆30Jun 13, 2022Updated 4 years ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆360Dec 2, 2025Updated 7 months ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆72May 13, 2026Updated last month
- SystemVerilog file list pruner☆19Mar 2, 2026Updated 4 months ago
- ☆98May 20, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Mar 28, 2025Updated last year
- Database and Tool Framework for EDA☆126Jan 25, 2021Updated 5 years ago
- An open-source static random access memory (SRAM) compiler.☆1,086Jun 27, 2026Updated last week
- A padring generator for ASICs☆26May 17, 2023Updated 3 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 4 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆464Jul 1, 2026Updated last week
- Benchmarks for Yosys development☆24Feb 17, 2020Updated 6 years ago
- SystemVerilog to Verilog conversion☆739Mar 28, 2026Updated 3 months ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆232Oct 26, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆798Jun 15, 2024Updated 2 years ago
- Mirror of tachyon-da cvc Verilog simulator☆55Mar 16, 2026Updated 3 months ago
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Sep 24, 2021Updated 4 years ago
- ☆37Sep 19, 2024Updated last year
- A Flyweight MBIST Block - FPGA synthesizable, Multi-algorithm integrated☆19Jan 27, 2019Updated 7 years ago
- Verilog hardware abstraction library☆54Jun 29, 2026Updated last week
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆19Dec 5, 2022Updated 3 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆706Dec 26, 2025Updated 6 months ago
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated 11 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- A Standalone Structural Verilog Parser☆98Mar 31, 2022Updated 4 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆14Jul 22, 2020Updated 5 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆30Jan 21, 2025Updated last year
- draws an SVG schematic from a JSON netlist☆802Jan 25, 2024Updated 2 years ago
- ☆15May 24, 2025Updated last year
- Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.☆3,584Oct 28, 2024Updated last year
- Fully Open Source FASOC generators built on top of open-source EDA tools☆338Oct 22, 2025Updated 8 months ago