Delay Calculation ToolKit
☆32Aug 7, 2022Updated 3 years ago
Alternatives and similar repositories for dctk
Users that are interested in dctk are comparing it to the libraries listed below
Sorting:
- Gate-level timing estimation toolkit☆25Apr 11, 2022Updated 3 years ago
- Optimal gate sizing of digital circuits using geometric programming☆11Aug 18, 2016Updated 9 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆690Dec 26, 2025Updated 2 months ago
- EDA physical synthesis optimization kit☆64Nov 13, 2023Updated 2 years ago
- ☆44Jan 26, 2020Updated 6 years ago
- Analog IC symmetry extraction benchmark of AncstrGNN☆10Aug 19, 2024Updated last year
- ☆43Nov 28, 2022Updated 3 years ago
- ☆25Dec 8, 2025Updated 2 months ago
- ☆14Jul 19, 2024Updated last year
- A High-performance Timing Analysis Tool for VLSI Systems☆10Feb 11, 2021Updated 5 years ago
- ☆26Apr 24, 2021Updated 4 years ago
- DATC RDF☆49Jul 31, 2020Updated 5 years ago
- A free standard cell library for SDDS-NCL circuits☆28Mar 3, 2023Updated 3 years ago
- Public repository for Task 6 of OpenROAD project. ML-based PDN synthesis and optimization.☆36Jul 6, 2023Updated 2 years ago
- ☆102Updated this week
- ☆33Dec 16, 2021Updated 4 years ago
- discrete gate sizing☆14Nov 23, 2020Updated 5 years ago
- ☆16Jul 16, 2020Updated 5 years ago
- The Berkeley Verilog-A Parser and Processor☆15Mar 24, 2017Updated 8 years ago
- This package provides a gnucap based qucsator implementation.☆15Feb 3, 2026Updated last month
- Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter☆23Feb 24, 2026Updated last week
- ☆20Apr 19, 2024Updated last year
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Dec 5, 2022Updated 3 years ago
- Pulsar asynchronous synthesis framework☆13Apr 2, 2021Updated 4 years ago
- Bounded-Skew DME v1.3☆15Aug 3, 2018Updated 7 years ago
- OpenSTA engine☆551Updated this week
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Jan 13, 2023Updated 3 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆40Jun 10, 2021Updated 4 years ago
- EPFL logic synthesis benchmarks☆231Nov 18, 2025Updated 3 months ago
- Benchmarks for Approximate Circuit Synthesis☆17Aug 2, 2020Updated 5 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- ☆51Apr 8, 2024Updated last year
- Annealing-based PCB placement tool☆40May 26, 2020Updated 5 years ago
- DATC Robust Design Flow.☆35Jan 21, 2020Updated 6 years ago
- ☆17Dec 10, 2018Updated 7 years ago
- An open multiple patterning framework☆83May 17, 2024Updated last year
- Reference for https://int21.io/post/50-million-points/index.html☆20Oct 2, 2018Updated 7 years ago
- GDS visualization, geometry analysis, and parallelized capacitance extraction at field-solver accuracy. MS thesis project.☆25Jul 1, 2024Updated last year
- An open-source EDA infrastructure and tools from netlist to GDS☆490Jan 10, 2026Updated last month