zao111222333 / liberty-dbLinks
Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter
☆18Updated this week
Alternatives and similar repositories for liberty-db
Users that are interested in liberty-db are comparing it to the libraries listed below
Sorting:
- Integrated Circuit Layout☆54Updated 6 months ago
- ☆25Updated 4 years ago
- ☆45Updated last year
- VLSI placement and routing tool☆14Updated last year
- A Standalone Structural Verilog Parser☆97Updated 3 years ago
- Interchange formats for chip design.☆31Updated 3 months ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- ☆85Updated 2 months ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆56Updated 3 years ago
- A LEF/DEF Utility.☆31Updated 6 years ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆112Updated last week
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62Updated last year
- Delay Calculation ToolKit☆32Updated 3 years ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- Intel's Analog Detailed Router☆39Updated 6 years ago
- ☆83Updated last week
- Database and Tool Framework for EDA☆117Updated 4 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆58Updated 5 years ago
- Tapeouts done using OpenFASOC☆11Updated last year
- Mirror of Synopsys's Liberty parser library☆24Updated 7 years ago
- EDA physical synthesis optimization kit☆60Updated last year
- UCSD Detailed Router☆90Updated 4 years ago
- ☆74Updated 2 months ago
- AMC: Asynchronous Memory Compiler☆50Updated 5 years ago
- ☆22Updated 4 years ago
- GPU-based logic synthesis tool☆90Updated 3 weeks ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆175Updated 3 months ago
- Determines the modules declared and instantiated in a SystemVerilog file☆47Updated 11 months ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 5 years ago
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆102Updated 7 months ago