zao111222333 / liberty-dbLinks
Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter
☆16Updated last week
Alternatives and similar repositories for liberty-db
Users that are interested in liberty-db are comparing it to the libraries listed below
Sorting:
- Integrated Circuit Layout☆54Updated 4 months ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆74Updated this week
- 21st century electronic design automation tools, written in Rust.☆30Updated this week
- Structural Netlist API (and more) for EDA post synthesis flow development☆111Updated this week
- Interchange formats for chip design.☆31Updated 2 months ago
- ☆25Updated 4 years ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆47Updated 6 months ago
- An innovative Verilog-A compiler☆159Updated 10 months ago
- Logic circuit analysis and optimization☆43Updated last week
- Coriolis VLSI EDA Tool (LIP6)☆68Updated this week
- Hardware generator debugger☆74Updated last year
- Rust Test Bench - write HDL tests in Rust.☆23Updated 2 years ago
- Hardware Description Library☆81Updated 3 months ago
- Verilog-A simulation models☆74Updated this week
- A Standalone Structural Verilog Parser☆93Updated 3 years ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆120Updated last month
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- A Verilog Filelist parser in Rust☆11Updated 3 years ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62Updated last year
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆101Updated 5 months ago
- Determines the modules declared and instantiated in a SystemVerilog file☆46Updated 9 months ago
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆35Updated this week
- high-performance RTL simulator☆168Updated last year
- VLSI placement and routing tool☆14Updated last year
- Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.☆55Updated 4 years ago
- A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding☆21Updated 4 months ago
- ☆76Updated 3 weeks ago
- ☆44Updated last year
- SystemVerilog language server client for Visual Studio Code☆21Updated 2 years ago
- An automatic clock gating utility☆50Updated 2 months ago