zao111222333 / liberty-dbLinks
Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter
☆14Updated last week
Alternatives and similar repositories for liberty-db
Users that are interested in liberty-db are comparing it to the libraries listed below
Sorting:
- 21st century electronic design automation tools, written in Rust.☆30Updated last week
- Integrated Circuit Layout☆53Updated 3 months ago
- Logic circuit analysis and optimization☆39Updated 7 months ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆65Updated 3 weeks ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆44Updated 5 months ago
- Interchange formats for chip design.☆31Updated 3 weeks ago
- ☆24Updated 4 years ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆102Updated this week
- ☆22Updated 4 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Updated 6 years ago
- Coriolis VLSI EDA Tool (LIP6)☆67Updated last week
- Verilog AST☆21Updated last year
- Determines the modules declared and instantiated in a SystemVerilog file☆44Updated 8 months ago
- An automatic clock gating utility☆47Updated last month
- A SystemVerilog source file pickler.☆57Updated 7 months ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆60Updated last year
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆55Updated 2 years ago
- Qrouter detail router for digital ASIC designs☆57Updated last month
- Gate-level timing estimation toolkit☆23Updated 3 years ago
- ☆31Updated last year
- A LEF/DEF Utility.☆30Updated 5 years ago
- ☆13Updated 4 years ago
- Technology file parser in Rust☆12Updated 4 years ago
- A Standalone Structural Verilog Parser☆92Updated 3 years ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- This is a SpyDrNet Plugin for a physical design related transformations☆12Updated 2 weeks ago
- A new Hardware Design Language that keeps you in the driver's seat☆80Updated this week
- Verilator Porcelain☆47Updated last year
- ☆25Updated 2 years ago