zao111222333 / liberty-dbView external linksLinks
Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter
☆23Feb 3, 2026Updated 2 weeks ago
Alternatives and similar repositories for liberty-db
Users that are interested in liberty-db are comparing it to the libraries listed below
Sorting:
- Library Exchange Format (LEF) and Design Exchange Format (DEF)☆24Aug 13, 2020Updated 5 years ago
- A single-script repo for a script to turn a calibre layer file to a KLayout .lyp file☆13Sep 3, 2018Updated 7 years ago
- Integration test for entire CGRA flow☆12Jan 17, 2020Updated 6 years ago
- Open source Photonics PDK for VTT's 3 um SOI platform.☆14May 26, 2025Updated 8 months ago
- gdsfactory implementation of LXT PDK.☆16Jan 16, 2026Updated last month
- VLSI placement and routing tool☆15Dec 20, 2025Updated last month
- Integrated Circuit Layout☆57Feb 25, 2025Updated 11 months ago
- ☆95Jun 20, 2025Updated 7 months ago
- Chip on Wafer on Substrate (CoWoS) Guide☆47Feb 1, 2022Updated 4 years ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆134Feb 10, 2026Updated last week
- Currently only a playground for rust, wgpu, openlayers web mapping combo☆19Updated this week
- Gate-level timing estimation toolkit☆25Apr 11, 2022Updated 3 years ago
- Parametric NEM/MEM relay design with layout generation (KLayout: GDSII), FEM (Ansys/COMSOL), SPICE models, Liberty models, & more☆23Jun 8, 2024Updated last year
- Doug is a WIP semi-automated to full manual VLSI Analog and Mixed Signal CAD design tool built with Bevy and Layout21☆18Jan 12, 2025Updated last year
- Logic circuit analysis and optimization☆45Feb 2, 2026Updated 2 weeks ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆19Jul 22, 2020Updated 5 years ago
- GDS visualization, geometry analysis, and parallelized capacitance extraction at field-solver accuracy. MS thesis project.☆25Jul 1, 2024Updated last year
- ideas and eda software for vlsi design☆51Feb 6, 2026Updated last week
- Yosys plugin for logic locking and supply-chain security☆23Apr 5, 2025Updated 10 months ago
- Hardware implementation of ORAM☆24Jul 12, 2017Updated 8 years ago
- ☆24Dec 16, 2020Updated 5 years ago
- An innovative Verilog-A compiler☆180Aug 20, 2024Updated last year
- ☆26Apr 24, 2021Updated 4 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆59Aug 7, 2022Updated 3 years ago
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆103Mar 6, 2022Updated 3 years ago
- An innovative Verilog-A compiler - reloaded☆37Jan 21, 2026Updated 3 weeks ago
- ☆24May 6, 2023Updated 2 years ago
- A highly scalable architecture to start your digital product in clean way☆13Jan 29, 2024Updated 2 years ago
- Delay Calculation ToolKit☆32Aug 7, 2022Updated 3 years ago
- Database and Tool Framework for EDA☆123Jan 25, 2021Updated 5 years ago
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆37Jun 17, 2025Updated 8 months ago
- An analytical VLSI placer☆31Nov 22, 2021Updated 4 years ago
- Parasitic Extraction for KLayout☆39Feb 3, 2026Updated 2 weeks ago
- An advanced header-only exact synthesis library☆31Nov 24, 2022Updated 3 years ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆31Feb 25, 2022Updated 3 years ago
- IRSIM switch-level simulator for digital circuits☆36Nov 13, 2025Updated 3 months ago
- A LEF/DEF Utility.☆33Aug 15, 2019Updated 6 years ago
- KLayout Web Viewer☆33Feb 21, 2025Updated 11 months ago
- Interchange formats for chip design.☆36Feb 3, 2026Updated 2 weeks ago