Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter
☆31Feb 24, 2026Updated 8 months ago
Alternatives and similar repositories for liberty-db
Users that are interested in liberty-db are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆23Sep 28, 2026Updated last month
- Delay Calculation ToolKit☆32Aug 7, 2022Updated 4 years ago
- Solution for 2022 ICCAD Problem D: Wirelength Driven Detailed Macro Placement☆15Nov 14, 2024Updated last year
- Gate-level timing estimation toolkit☆25Apr 11, 2022Updated 4 years ago
- ☆14Jun 21, 2026Updated 4 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Database and Tool Framework for EDA☆128Jan 25, 2021Updated 5 years ago
- ☆113Jun 20, 2025Updated last year
- ☆19Jun 12, 2026Updated 4 months ago
- Spirit X3 Liberty Format Parser. opensourceliberty.org for more info.☆10Jan 5, 2023Updated 3 years ago
- Library Exchange Format (LEF) and Design Exchange Format (DEF)☆28Aug 13, 2020Updated 6 years ago
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆71Sep 22, 2026Updated last month
- App store and stack manager for FreeBSD or Linux: run daemonless OCI apps as jails on podman or AppJail from one static binary☆13Updated this week
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆148Oct 25, 2026Updated last week
- Using e-graphs to synthesize netlists from boolean logic.☆14Jul 26, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Logic circuit analysis and optimization☆53Feb 2, 2026Updated 9 months ago
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Nov 19, 2024Updated last year
- A single-script repo for a script to turn a calibre layer file to a KLayout .lyp file☆16Sep 3, 2018Updated 8 years ago
- (WIP) Open-source Rust gate-level EDA infrastructure: parsers and databases☆23May 2, 2026Updated 6 months ago
- cpp parser for reading a VCD (value change dump) file☆10Jul 15, 2013Updated 13 years ago
- Mirror of Synopsys's Liberty parser library☆24Jul 6, 2018Updated 8 years ago
- Open-source EDA framework for RTL elaboration, netlist analysis, and transformation, with C++ and Python APIs☆169Updated this week
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- Coriolis VLSI EDA Tool (LIP6)☆94Updated this week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Integrated Circuit Layout☆63Feb 25, 2025Updated last year
- FPGA synthesis tool powered by equality saturation and program synthesis.☆17Jan 9, 2026Updated 9 months ago
- Zero Board Computer semihosting device reference implementation☆11Jun 13, 2026Updated 4 months ago
- ☆11Jul 16, 2025Updated last year
- Circuit Release for Analog Test Cases from UW IDEA project☆10Sep 14, 2022Updated 4 years ago
- ☆15Jul 19, 2024Updated 2 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆40Updated this week
- EDA physical synthesis optimization kit☆70Nov 13, 2023Updated 2 years ago
- 📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC☆23Jun 26, 2023Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- GDS visualization, geometry analysis, and parallelized capacitance extraction at field-solver accuracy. MS thesis project.☆26Jul 1, 2024Updated 2 years ago
- The Berkeley Verilog-A Parser and Processor☆15Mar 24, 2017Updated 9 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆46Jan 13, 2023Updated 3 years ago
- A small library for BDD manipulation in Rust. Part of the BioDivine toolset.☆27Jul 5, 2026Updated 4 months ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆255Updated this week
- Integration test for entire CGRA flow☆12Jan 17, 2020Updated 6 years ago
- GL0AM GPU Accelerated Gate Level Logic Simulator☆33Feb 11, 2026Updated 8 months ago