Alternatives and similar repositories for liberty-db

Users that are interested in liberty-db are comparing it to the libraries listed below

• dan-fritchman / Layout21
  Integrated Circuit Layout
  ☆57Updated 9 months ago
• Ravenslofty / librecell
  ☆26Updated 4 years ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆33Updated last week
• Coloquinte / PlaceRoute
  VLSI placement and routing tool
  ☆15Updated 3 weeks ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆63Updated 2 years ago
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆33Updated 6 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆18Updated 5 years ago
• NVlabs / INSTA
  ☆90Updated 6 months ago
• Vlsir / Vlsir
  Interchange formats for chip design.
  ☆36Updated 7 months ago
• idea-fasoc / openfasoc-tapeouts
  Tapeouts done using OpenFASOC
  ☆14Updated last month
• ABKGroup / RosettaStone
  ☆32Updated 3 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆51Updated 5 years ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆123Updated this week
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆62Updated last year
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆42Updated this week
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆99Updated 3 years ago
• eclufsc / libertyParser
  Mirror of Synopsys's Liberty parser library
  ☆24Updated 7 years ago
• ABKGroup / PROBE3.0
  ☆49Updated last year
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆45Updated 3 months ago
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆103Updated last week
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆58Updated 3 years ago
• ganeshgore / spydrnet-physical
  This is a SpyDrNet Plugin for a physical design related transformations
  ☆16Updated 6 months ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆39Updated 6 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆58Updated 5 years ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆49Updated last year
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆88Updated 8 months ago
• The-OpenROAD-Project / OpenRCX
  ☆23Updated 5 years ago
• parallaxsw / OpenSTA
  ☆97Updated this week
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆59Updated 11 months ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆32Updated 3 years ago