Material for OpenROAD Tutorial at DAC 2020
☆47Dec 8, 2022Updated 3 years ago
Alternatives and similar repositories for DAC-2020-Tutorial
Users that are interested in DAC-2020-Tutorial are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- DATC Robust Design Flow.☆36Jan 21, 2020Updated 6 years ago
- DATC RDF☆49Jul 31, 2020Updated 5 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆50Nov 18, 2024Updated last year
- Rsyn – An Extensible Physical Synthesis Framework☆139Jul 20, 2024Updated last year
- Macro placement tool for OpenROAD flow☆27Aug 13, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Database and Tool Framework for EDA☆125Jan 25, 2021Updated 5 years ago
- Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian☆45Feb 17, 2021Updated 5 years ago
- Open Source Detailed Placement engine☆13Feb 19, 2020Updated 6 years ago
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆21Aug 20, 2019Updated 6 years ago
- Python version of tools to work with AIG formatted files☆12May 20, 2025Updated last year
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆639Updated this week
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆62Aug 10, 2020Updated 5 years ago
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆14Jun 9, 2021Updated 4 years ago
- The first large scale formally verified reasoning dataset for Verilog☆21May 16, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆145Mar 20, 2023Updated 3 years ago
- VGA LCD Core (OpenCores)☆15May 22, 2018Updated 8 years ago
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆2,679Updated this week
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆94Aug 22, 2024Updated last year
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆19Jul 22, 2020Updated 5 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Feb 18, 2020Updated 6 years ago
- RePlAce global placement tool☆252Aug 13, 2020Updated 5 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆61Aug 7, 2022Updated 3 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆21Nov 18, 2022Updated 3 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆24Aug 11, 2020Updated 5 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆16Jun 23, 2020Updated 5 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Nov 2, 2021Updated 4 years ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Aug 25, 2021Updated 4 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆121Jul 31, 2021Updated 4 years ago
- EDA physical synthesis optimization kit☆67Nov 13, 2023Updated 2 years ago
- KLayout technology files for FreePDK45☆24Jun 12, 2021Updated 4 years ago
- nextpnr portable FPGA place and route tool☆11Nov 30, 2020Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A High-performance Timing Analysis Tool for VLSI Systems☆696Dec 26, 2025Updated 4 months ago
- UCSD Detailed Router☆97Jan 5, 2021Updated 5 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆23Oct 24, 2023Updated 2 years ago
- EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!☆76Jan 6, 2023Updated 3 years ago
- Benchmarks for Yosys development☆24Feb 17, 2020Updated 6 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆166Apr 1, 2026Updated last month
- This library contains rectilinear spanning graph construction, finding minimum spanning tree and an implementation of binary search tree☆10Aug 22, 2015Updated 10 years ago