The-OpenROAD-Project / PCB-PR-AppLinks
☆17Updated 5 years ago
Alternatives and similar repositories for PCB-PR-App
Users that are interested in PCB-PR-App are comparing it to the libraries listed below
Sorting:
- Power grid analysis☆20Updated 5 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆59Updated 5 years ago
- Annealing-based PCB placement tool☆39Updated 5 years ago
- ☆34Updated 5 years ago
- Macro placement tool for OpenROAD flow☆24Updated 5 years ago
- Global Router Built for ICCAD Contest 2019☆33Updated 5 years ago
- DATC Robust Design Flow.☆36Updated 5 years ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 5 years ago
- VLSI EDA Global Router☆79Updated 7 years ago
- UCSD Detailed Router☆94Updated 5 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Updated 6 years ago
- Open Source Detailed Placement engine☆12Updated 5 years ago
- DATC RDF☆50Updated 5 years ago
- Benchmark Generator for Global Routing☆12Updated 6 years ago
- Flute3 is an open-source rectilinear Steiner minimum tree heuristic from Iowa State, with UFRGS improvements☆29Updated 5 years ago
- ☆16Updated 5 years ago
- ☆32Updated 3 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆141Updated 2 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆141Updated 2 years ago
- ☆77Updated 3 weeks ago
- Optimal gate sizing of digital circuits using geometric programming☆11Updated 9 years ago
- Open Source Detailed Placement engine☆40Updated 6 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…☆21Updated 7 years ago
- ASTRAN - Automatic Synthesis of Transistor Networks☆66Updated 3 years ago
- GPU-based logic synthesis tool☆97Updated last month
- Steiner Shallow-Light Tree for VLSI Routing☆61Updated last year
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆13Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆75Updated last month
- Analog Placement Quality Prediction☆25Updated 2 years ago