Alternatives and similar repositories for Multi-Sink-Lee-Moore-Shortest-Path-Maze-Router:

Users that are interested in Multi-Sink-Lee-Moore-Shortest-Path-Maze-Router are comparing it to the libraries listed below

• gatelabdavis / RANE
  ☆22Updated last year
• yaohsiaopid / rtl2uspec
  ☆11Updated last year
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆20Updated this week
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated last year
• VP-Vibes / VPV-Peripherals
  Library of example SystemC/TLM peripherals for various SoCs based on the SCS library
  ☆12Updated this week
• cgfandia / PathfinderAlgorithm
  Pathfinder routing algorithm practice
  ☆12Updated 7 years ago
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆22Updated 8 months ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• msoeken / kitty
  C++ truth table library
  ☆51Updated 11 months ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated this week
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆22Updated last year
• zslwyuan / Light-HLS
  Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)
  ☆59Updated 2 years ago
• The-OpenROAD-Project / Birds-of-a-Feather-Open-Source-Academic-EDA-Software
  Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !
  ☆12Updated 5 years ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆18Updated 4 months ago
• jianyicheng / HLS-benchmarks
  Benchmarks for High-Level Synthesis
  ☆10Updated last year
• chengyinwu / QuteRTL
  QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification
  ☆14Updated 8 years ago
• ben-marshall / verilog-dot
  A simple dot file / graph generator for Verilog syntax trees.
  ☆21Updated 8 years ago
• tum-ei-eda / vrtlmod
  vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/C…
  ☆13Updated 5 months ago
• jianyicheng / iiProver
  An LLVM pass to prove that an II works for the given loop for Vitis HLS
  ☆11Updated 3 years ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆29Updated last year
• ycunxi / FLowGen-CNNs-DAC18
  ☆14Updated 6 years ago
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 3 years ago
• janweinstock / or1kmvp
  An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM
  ☆10Updated last year
• The-OpenROAD-Project / PcbRouter
  ☆29Updated 4 years ago
• chengyinwu / V3
  An Extensible Framework for Hardware Verification and Debugging
  ☆18Updated 2 years ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆30Updated 4 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• wincle626 / HLS_Legup
  ☆26Updated 7 years ago
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆35Updated last year
• The-OpenROAD-Project / micro2022tutorial
  Website for the OpenROAD tutorial held at the MICRO 2022 conference
  ☆26Updated 2 years ago