Alternatives and similar repositories for Birds-of-a-Feather-Open-Source-Academic-EDA-Software

Users that are interested in Birds-of-a-Feather-Open-Source-Academic-EDA-Software are comparing it to the libraries listed below

• The-OpenROAD-Project / OpenDP
  Open Source Detailed Placement engine
  ☆12Updated 5 years ago
• The-OpenROAD-Project / TritonMacroPlace
  Macro placement tool for OpenROAD flow
  ☆23Updated 5 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• The-OpenROAD-Project / TritonSizer
  UCSD Sizer for leakage/dynamic power recovery, timing recovery
  ☆18Updated 6 years ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 5 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• The-OpenROAD-Project / KicadParser
  ☆16Updated 5 years ago
• The-OpenROAD-Project / OpenROAD-Cloud
  The source code that empowers OpenROAD Cloud
  ☆12Updated 5 years ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆62Updated last year
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• The-OpenROAD-Project / PDNSim
  Power grid analysis
  ☆19Updated 5 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 10 years ago
• klasnordmark / openlane-examples
  Examples from the Openlane repository, adapted as Fusesoc cores
  ☆12Updated 4 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated 6 months ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆19Updated 11 months ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆58Updated 5 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆29Updated 2 years ago
• cuhk-eda / ripple-fpga
  RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
  ☆90Updated 5 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• geochrist / dctk
  Delay Calculation ToolKit
  ☆32Updated 3 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• rachelselinar / ReGDS-Logic-Gate-Extraction
  A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …
  ☆31Updated last year
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• lsils / percy
  C++ header-only exact synthesis library
  ☆18Updated 2 years ago
• The-OpenROAD-Project / OpenDB
  Database and Tool Framework for EDA
  ☆118Updated 4 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 3 years ago
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆57Updated 3 years ago