The-OpenROAD-Project / Birds-of-a-Feather-Open-Source-Academic-EDA-Software

Related projects ⓘ

Alternatives and complementary repositories for Birds-of-a-Feather-Open-Source-Academic-EDA-Software

• The-OpenROAD-Project / OpenDP
  Open Source Detailed Placement engine
  ☆11Updated 4 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 3 months ago
• The-OpenROAD-Project / TritonSizer
  UCSD Sizer for leakage/dynamic power recovery, timing recovery
  ☆17Updated 5 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆39Updated 4 years ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆23Updated 4 years ago
• The-OpenROAD-Project / TritonMacroPlace
  Macro placement tool for OpenROAD flow
  ☆21Updated 4 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆21Updated 4 years ago
• The-OpenROAD-Project-Attic / lef
  Si2 LEF parser
  ☆9Updated 3 years ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆26Updated 2 years ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆18Updated last week
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆16Updated 2 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆53Updated 4 years ago
• The-OpenROAD-Project / KicadParser
  ☆13Updated 4 years ago
• The-OpenROAD-Project / OpenRCX
  ☆19Updated 3 years ago
• chipsalliance / UHDM-integration-tests
  ☆30Updated last year
• bluecheetah / bag
  BAG framework
  ☆41Updated 3 months ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆46Updated 9 years ago
• lsils / percy
  C++ header-only exact synthesis library
  ☆15Updated last year
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• The-OpenROAD-Project / PDNSim
  Power grid analysis
  ☆17Updated 4 years ago
• The-OpenROAD-Project / OpenROAD-Cloud
  The source code that empowers OpenROAD Cloud
  ☆11Updated 4 years ago
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆51Updated 2 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆52Updated 4 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆56Updated last month
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆55Updated 5 months ago
• aolofsson / POSH
  ☆39Updated 4 years ago
• The-OpenROAD-Project / PcbRouter
  ☆24Updated 4 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆34Updated 7 months ago
• rachelselinar / ReGDS-Logic-Gate-Extraction
  A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …
  ☆27Updated 2 months ago
• The-OpenROAD-Project-Attic / Resizer
  ☆13Updated 5 years ago