The-OpenROAD-Project / Birds-of-a-Feather-Open-Source-Academic-EDA-Software
Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !
☆12Updated 5 years ago
Alternatives and similar repositories for Birds-of-a-Feather-Open-Source-Academic-EDA-Software:
Users that are interested in Birds-of-a-Feather-Open-Source-Academic-EDA-Software are comparing it to the libraries listed below
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Updated 5 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 4 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 6 months ago
- Open Source Detailed Placement engine☆11Updated 4 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- Macro placement tool for OpenROAD flow☆23Updated 4 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆22Updated 4 years ago
- Benchmarks for Yosys development☆23Updated 4 years ago
- The source code that empowers OpenROAD Cloud☆12Updated 4 years ago
- Power grid analysis☆19Updated 4 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆29Updated last month
- Extended and external tests for Verilator testing☆16Updated last week
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- ☆20Updated 3 years ago
- ☆22Updated 4 years ago
- ☆13Updated 4 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆56Updated 7 months ago
- SRAM☆8Updated 4 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- ☆15Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated this week
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆22Updated 4 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- Global Router Built for ICCAD Contest 2019☆29Updated 4 years ago
- ☆40Updated 4 years ago
- A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …☆28Updated 4 months ago