Alternatives and similar repositories for GlobalRoutingProblemGenerator

Users that are interested in GlobalRoutingProblemGenerator are comparing it to the libraries listed below

• UTDA-group / BoxRouter
  BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…
  ☆21Updated 6 years ago
• cuhk-eda / REST
  REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)
  ☆55Updated 3 years ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆31Updated 5 years ago
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆47Updated 3 months ago
• magical-eda / UT-AnLay
  Analog Placement Quality Prediction
  ☆21Updated 2 years ago
• LQY404 / EDA-info
  the awesome work, project and lab of EDA (Electronic Design Automation). continue update...
  ☆23Updated 8 months ago
• krzhu / abcRL
  MLCAD 2020: Reinforcement for logic optimization sequence exploration
  ☆28Updated 4 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 4 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• Chenghao-Yang / awesome-ml4ls
  Awesome machine learning for logic synthesis
  ☆26Updated 2 years ago
• TimingPredict / Dataset
  Timing prediction dataset download and instructions.
  ☆15Updated last year
• krzhu / abc_py
  Simple Python interface for ABC
  ☆23Updated last year
• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆21Updated last year
• baloneymath / AncstrGNN
  ☆16Updated 3 years ago
• CMACH508 / DeepTH
  ☆14Updated 11 months ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆29Updated last year
• gaflach / usizer
  discrete gate sizing
  ☆14Updated 4 years ago
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆74Updated 8 months ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆39Updated last year
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆73Updated 7 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆38Updated 5 years ago
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆18Updated last month
• IntelLabs / parsac
  This is the implementation of the Parallel Simulated Annealing with Constraints (PARSAC) algorithm
  ☆12Updated 9 months ago
• chengengjie / salt
  Steiner Shallow-Light Tree for VLSI Routing
  ☆51Updated 10 months ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆54Updated 4 years ago
• UMN-EDA / BeGAN-benchmarks
  ☆24Updated last year
• parkerluxu / awesome-Analog-IC-Design-Automation
  awesome-Analog-IC-Design-Automation
  ☆34Updated 2 years ago
• The-OpenROAD-Project-Attic / flute3
  Flute3 is an open-source rectilinear Steiner minimum tree heuristic from Iowa State, with UFRGS improvements
  ☆25Updated 4 years ago
• aspdac-submission-pcb-layout / PCBBenchmarks
  ☆22Updated 4 years ago