Alternatives and similar repositories for GlobalRoutingProblemGenerator

Users that are interested in GlobalRoutingProblemGenerator are comparing it to the libraries listed below

• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• cuhk-eda / REST
  REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)
  ☆59Updated 3 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆79Updated 7 years ago
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆141Updated 2 years ago
• Chenghao-Yang / awesome-ml4ls
  Awesome machine learning for logic synthesis
  ☆30Updated 3 years ago
• krzhu / abcRL
  MLCAD 2020: Reinforcement for logic optimization sequence exploration
  ☆29Updated 5 years ago
• scale-lab / DRiLLS
  DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)
  ☆115Updated 2 years ago
• UTDA-group / BoxRouter
  BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…
  ☆21Updated 7 years ago
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆14Updated last year
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆33Updated 5 years ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆141Updated 2 years ago
• magical-eda / UT-AnLay
  Analog Placement Quality Prediction
  ☆25Updated 2 years ago
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆53Updated 11 months ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆32Updated 2 years ago
• The-OpenROAD-Project / PCB-PR-App
  ☆17Updated 5 years ago
• ABKGroup / PlacementEssentialReadings
  ☆60Updated 4 years ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• CODA-Team / AncstrGNN_benchmark
  Analog IC symmetry extraction benchmark of AncstrGNN
  ☆10Updated last year
• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆24Updated 2 years ago
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆22Updated 9 months ago
• Daikon-Sun / Routing-Visualization
  Routing Visualization for Physical Design
  ☆19Updated 7 years ago
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆85Updated last year
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆36Updated 5 years ago
• IntelLabs / FloorSet
  ☆77Updated this week
• Yu-Maryland / Verilog-to-PyG
  ☆29Updated last year
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆32Updated 4 years ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆59Updated 7 months ago
• krzhu / abc_py
  Simple Python interface for ABC
  ☆26Updated 2 years ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆46Updated last year
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆97Updated last month